## Abstract

In the standard MOSFET description of the drain current I
_{D} as a function of applied gate voltage V
_{GS}, the subthreshold swing SS(T)≡ dV
_{GS}/d log I
_{D} has a fundamental lower limit as a function of temperature T given by SS(T)= ln 10 k
_{B} T/e. However, recent low-temperature studies of different advanced CMOS technologies have reported SS(4 K or lower) values that are at least an order of magnitude larger. Here, we present and analyze the saturation of SS(T) in 28 nm fully-depleted silicon-on-insulator (FD-SOI) devices for both n- and p-type MOSFETs of different gate oxide thicknesses and gate lengths down to 4 K. Until now, the increase of interface-trap density close to the band edge as temperature decreases has been put forward to understand the saturation. Here, an original explanation of the phenomenon is presented by considering a disorder-induced tail in the density of states at the conduction (valence) band edge for the calculation of the MOS channel transport by applying the Fermi-Dirac statistics. This results in a subthreshold I
_{D} ∼ e
^{eV GS/k B T 0} for T
_{0}=35 K with saturation value SS (T < T
_{0})= ln 10 k
_{B} T
_{0}/e. The proposed model adequately describes the experimental data of SS(T) from 300 down to 4 K using k
_{B} T
_{0} ≃ 3 meV for the width of the exponential tail and can also accurately describe SS(I
_{D}) within the whole subthreshold region. Our analysis allows a direct determination of the technology-dependent band-tail extension forming a crucial element in future compact modeling and the design of cryogenic circuits.

Original language | English |
---|---|

Article number | 8660508 |

Pages (from-to) | 784-787 |

Number of pages | 4 |

Journal | IEEE Electron Device Letters |

Volume | 40 |

Issue number | 5 |

DOIs | |

Publication status | Published - May 2019 |

MoE publication type | A1 Journal article-refereed |

## Keywords

- 28 nm FD-SOI
- Cryogenic electronics
- MOSFET
- band tail
- quantum computing
- subthreshold swing