Design-oriented modeling of 28 nm FDSOI CMOS technology down to 4.2 K for quantum computing

Arnout Beckers; Farzan Jazaeri; Heorhii Bohuslavskyi; Louis Hutin; Silvano De Franceschi; Christian Enz

doi:10.1109/ulis.2018.8354742

Design-oriented modeling of 28 nm FDSOI CMOS technology down to 4.2 K for quantum computing

Arnout Beckers, Farzan Jazaeri, Heorhii Bohuslavskyi, Louis Hutin, Silvano De Franceschi, Christian Enz

Not published at VTT

Research output: Chapter in Book/Report/Conference proceeding › Conference article in proceedings › Scientific › peer-review

40 Citations (Scopus)

Abstract

In this paper a commercial 28 nm FDSOI CMOS technology is characterized and modeled from room temperature down to 4.2 K. Here we explain the influence of incomplete ionization and interface traps on this technology starting from the fundamental device-physics. We then illustrate how these phenomena can be accounted for in circuit device-models. We find that the design-oriented simplified EKV model can accurately predict the impact of the temperature reduction on the transfer characteristics, back-gate sensitivity, and transconductance efficiency. The presented results aim at extending industry-standard compact models to cryogenic temperatures for the design of cryo-CMOS circuits implemented in a 28 nm FDSOI technology.

Original language	English
Title of host publication	2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2018
Editors	Viktor Sverdlov, Carlos Sampedro, Luca Donetti, Francisco Gamiz
Publisher	IEEE Institute of Electrical and Electronic Engineers
Pages	1-4
Number of pages	4
ISBN (Electronic)	978-1-5386-4811-7
DOIs	https://doi.org/10.1109/ulis.2018.8354742
Publication status	Published - Mar 2018
MoE publication type	A4 Article in a conference publication

Keywords

28 nm FDSOI
4.2 K
cryo-CMOS
cryoelectronics
cryogenic
quantum computing

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10.1109/ulis.2018.8354742

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Beckers, A., Jazaeri, F., Bohuslavskyi, H., Hutin, L., Franceschi, S. D., & Enz, C. (2018). Design-oriented modeling of 28 nm FDSOI CMOS technology down to 4.2 K for quantum computing. In V. Sverdlov, C. Sampedro, L. Donetti, & F. Gamiz (Eds.), 2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2018 (pp. 1-4). IEEE Institute of Electrical and Electronic Engineers. https://doi.org/10.1109/ulis.2018.8354742

Beckers, Arnout ; Jazaeri, Farzan ; Bohuslavskyi, Heorhii et al. / Design-oriented modeling of 28 nm FDSOI CMOS technology down to 4.2 K for quantum computing. 2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2018. editor / Viktor Sverdlov ; Carlos Sampedro ; Luca Donetti ; Francisco Gamiz. IEEE Institute of Electrical and Electronic Engineers, 2018. pp. 1-4

@inproceedings{b726c364fe814703a0703f7324eff615,

title = "Design-oriented modeling of 28 nm FDSOI CMOS technology down to 4.2 K for quantum computing",

abstract = "In this paper a commercial 28 nm FDSOI CMOS technology is characterized and modeled from room temperature down to 4.2 K. Here we explain the influence of incomplete ionization and interface traps on this technology starting from the fundamental device-physics. We then illustrate how these phenomena can be accounted for in circuit device-models. We find that the design-oriented simplified EKV model can accurately predict the impact of the temperature reduction on the transfer characteristics, back-gate sensitivity, and transconductance efficiency. The presented results aim at extending industry-standard compact models to cryogenic temperatures for the design of cryo-CMOS circuits implemented in a 28 nm FDSOI technology.",

keywords = "28 nm FDSOI, 4.2 K, cryo-CMOS, cryoelectronics, cryogenic, quantum computing",

author = "Arnout Beckers and Farzan Jazaeri and Heorhii Bohuslavskyi and Louis Hutin and Franceschi, {Silvano De} and Christian Enz",

note = "Publisher Copyright: {\textcopyright} 2018 IEEE.",

year = "2018",

month = mar,

doi = "10.1109/ulis.2018.8354742",

language = "English",

pages = "1--4",

editor = "Viktor Sverdlov and Carlos Sampedro and Luca Donetti and Francisco Gamiz",

booktitle = "2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2018",

publisher = "IEEE Institute of Electrical and Electronic Engineers",

address = "United States",

}

Beckers, A, Jazaeri, F, Bohuslavskyi, H, Hutin, L, Franceschi, SD & Enz, C 2018, Design-oriented modeling of 28 nm FDSOI CMOS technology down to 4.2 K for quantum computing. in V Sverdlov, C Sampedro, L Donetti & F Gamiz (eds), 2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2018. IEEE Institute of Electrical and Electronic Engineers, pp. 1-4. https://doi.org/10.1109/ulis.2018.8354742

Design-oriented modeling of 28 nm FDSOI CMOS technology down to 4.2 K for quantum computing. / Beckers, Arnout; Jazaeri, Farzan; Bohuslavskyi, Heorhii et al.
2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2018. ed. / Viktor Sverdlov; Carlos Sampedro; Luca Donetti; Francisco Gamiz. IEEE Institute of Electrical and Electronic Engineers, 2018. p. 1-4.

Research output: Chapter in Book/Report/Conference proceeding › Conference article in proceedings › Scientific › peer-review

TY - GEN

T1 - Design-oriented modeling of 28 nm FDSOI CMOS technology down to 4.2 K for quantum computing

AU - Beckers, Arnout

AU - Jazaeri, Farzan

AU - Bohuslavskyi, Heorhii

AU - Hutin, Louis

AU - Franceschi, Silvano De

AU - Enz, Christian

PY - 2018/3

Y1 - 2018/3

N2 - In this paper a commercial 28 nm FDSOI CMOS technology is characterized and modeled from room temperature down to 4.2 K. Here we explain the influence of incomplete ionization and interface traps on this technology starting from the fundamental device-physics. We then illustrate how these phenomena can be accounted for in circuit device-models. We find that the design-oriented simplified EKV model can accurately predict the impact of the temperature reduction on the transfer characteristics, back-gate sensitivity, and transconductance efficiency. The presented results aim at extending industry-standard compact models to cryogenic temperatures for the design of cryo-CMOS circuits implemented in a 28 nm FDSOI technology.

AB - In this paper a commercial 28 nm FDSOI CMOS technology is characterized and modeled from room temperature down to 4.2 K. Here we explain the influence of incomplete ionization and interface traps on this technology starting from the fundamental device-physics. We then illustrate how these phenomena can be accounted for in circuit device-models. We find that the design-oriented simplified EKV model can accurately predict the impact of the temperature reduction on the transfer characteristics, back-gate sensitivity, and transconductance efficiency. The presented results aim at extending industry-standard compact models to cryogenic temperatures for the design of cryo-CMOS circuits implemented in a 28 nm FDSOI technology.

KW - 28 nm FDSOI

KW - 4.2 K

KW - cryo-CMOS

KW - cryoelectronics

KW - cryogenic

KW - quantum computing

UR - http://www.scopus.com/inward/record.url?scp=85050927069&partnerID=8YFLogxK

U2 - 10.1109/ulis.2018.8354742

DO - 10.1109/ulis.2018.8354742

M3 - Conference article in proceedings

SP - 1

EP - 4

BT - 2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2018

A2 - Sverdlov, Viktor

A2 - Sampedro, Carlos

A2 - Donetti, Luca

A2 - Gamiz, Francisco

PB - IEEE Institute of Electrical and Electronic Engineers

ER -

Beckers A, Jazaeri F, Bohuslavskyi H, Hutin L, Franceschi SD, Enz C. Design-oriented modeling of 28 nm FDSOI CMOS technology down to 4.2 K for quantum computing. In Sverdlov V, Sampedro C, Donetti L, Gamiz F, editors, 2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2018. IEEE Institute of Electrical and Electronic Engineers. 2018. p. 1-4 doi: 10.1109/ulis.2018.8354742

Design-oriented modeling of 28 nm FDSOI CMOS technology down to 4.2 K for quantum computing

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