Designing NOCs with a parallel extension of c

    Research output: Chapter in Book/Report/Conference proceedingConference article in proceedingsScientificpeer-review


    As systems on chip are evolving to networks on chip (NOC) providing a unified communication infrastructure for a number of computational resources, being able to easily implement computational tasks as a parallel program that can be efficiently executed by multiple resources together is becoming increasingly important. Recent advances in thread-level parallel (TLP) architectures have made it possible to implement efficiently an easy-to-use synchronous shared memory programming model (Parallel Random Access Machine, PRAM) on a NOC. In this paper we describe a novel programming language, called e, for fine-grained TLP programming on synchronous shared memory NOC architectures realizing the PRAM model. The language uses a familiar c-like syntax and provides support for shared and private variables, arbitrary hierarchical groups of threads, and synchronous control structures. This allows a programmer to use various advanced TLP programming techniques like data parallelism, divide-and-conquer technique, different blocking techniques, and both synchronous and asynchronous programming style. We will also shortly experiment the e-language with real parallel programs using our experimental e-compiler and scalable Eclipse NOC architecture.
    Original languageEnglish
    Title of host publicationProceedings of the Forum on Specification and Design Languages
    PublisherEuropean Electronic Chip and Systems Design Initiative (ECSI)
    Publication statusPublished - 2004
    MoE publication typeNot Eligible
    EventForum on Specification and Design Languages, FDL 04 - Lille, France
    Duration: 13 Sept 200417 Sept 2004


    ConferenceForum on Specification and Design Languages, FDL 04


    • Networks on chip
    • system-on-a-chip
    • design language
    • parallel programming language
    • thread-level parallelism


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