High volume traffic presumes high-throughput routers that are connected together with high-speed links. Routers equipped with a number of high capacity links have to implement very powerful switch fabrics. Extending clock rates of a high performance switch fabric to line-cards leads to demanding electronics design and expensive line-card implementations even in cases when only moderate link-speeds are supported. Hence, innovations that allow switch fabric interfaces to operate at clock rates lower than those inside the switch core are welcome. This paper analyzes the interface between a line-card and a switch fabric to find dimensioning rules that enable lowered bit rates while maintaining loss-free operation of the switch fabric.
|Title of host publication||Proceedings of the IASTED International Conference on Communications and Computer Networks|
|Subtitle of host publication||Cambridge, MA, US, 4-6 November 2002|
|Place of Publication||Anaheim|
|ISBN (Print)||0-88986-329-6, 978-0-88986-329-3|
|Publication status||Published - 2002|
|MoE publication type||A4 Article in a conference publication|
- broadband communications
- modeling and simulations
Raatikainen, P. (2002). Dimensioning of switch fabric interfaces of high-throughput routers. In Proceedings of the IASTED International Conference on Communications and Computer Networks: Cambridge, MA, US, 4-6 November 2002 (pp. 269-274). Acta Press.