Direct wafer bonding for MEMS and microelectronics: Dissertation

Tommi Suni

Research output: ThesisDissertation

1 Citation (Scopus)

Abstract

Direct wafer bonding is a method for fabricating advanced substrates for microelectromechanical systems (MEMS) and integrated circuits (IC). The most typical example of such an advanced substrate is the silicon-on-insulator (SOI) wafer. SOI wafers offer many advantages over conventional silicon wafers. In IC technology, the switching speed of circuits fabricated on SOI is increased by 20-50% compared to circuits fabricated on a bulk Si wafer. The required operation voltage is lower in ICs on SOI than in ICs on a bulk silicon wafer, which decreases power consumption and chip heating. In the MEMS industry, the buried oxide layer works as a good sacrificial layer during release etching of diaphragms, beams etc. and offers an excellent etch stop layer for silicon etching. Direct wafer bonding can also be used in the fabrication of more complex structures than SOI. The wafers to be bonded can be of different materials, can contain patterns, and may have multiple layers or ready-made devices. This thesis reports on studies of direct wafer bonding and its use in various applications. Different bonding processes used in microelectronics are briefly described. The main focus of this thesis is on the plasma activation-based low temperature bonding process, and on the control of bond strength by surface preparation. A novel method for bond strength measurement is introduced. This method, based on buried oxide etching, is presented and compared with other methods used in evaluating bond quality. This thesis also contains results on research of different applications requiring direct wafer bonding. Heterogeneous integration, pre-processed SOI fabrication, and wafer scale packaging are the main application topics.
Original languageEnglish
QualificationDoctor Degree
Awarding Institution
  • Aalto University
Supervisors/Advisors
  • Lehto, Ari, Supervisor, External person
Award date18 Aug 2006
Place of PublicationEspoo
Publisher
Print ISBNs951-38-6851-6
Electronic ISBNs951-38-6852-4
Publication statusPublished - 2006
MoE publication typeG5 Doctoral dissertation (article)

Fingerprint

Wafer bonding
Microelectronics
MEMS
Silicon
Etching
Silicon wafers
Integrated circuits
Fabrication
Oxides
Networks (circuits)
Substrates
Diaphragms
Packaging
Electric power utilization
Chemical activation
Plasmas
Heating
Electric potential

Keywords

  • direct wafer bonding
  • MEMS
  • microelectronics
  • microelectromechanical systems
  • SOI
  • silicon-on-insulator
  • integrated circuits
  • bond strength measurement
  • heterogeneous integration
  • pre-processed SOI fabrication
  • wafer-scale packaging
  • plasma activation

Cite this

Suni, T. (2006). Direct wafer bonding for MEMS and microelectronics: Dissertation. Espoo: VTT Technical Research Centre of Finland.
Suni, Tommi. / Direct wafer bonding for MEMS and microelectronics : Dissertation. Espoo : VTT Technical Research Centre of Finland, 2006. 140 p.
@phdthesis{b88f61b1c19f47c09f876102fb7e0011,
title = "Direct wafer bonding for MEMS and microelectronics: Dissertation",
abstract = "Direct wafer bonding is a method for fabricating advanced substrates for microelectromechanical systems (MEMS) and integrated circuits (IC). The most typical example of such an advanced substrate is the silicon-on-insulator (SOI) wafer. SOI wafers offer many advantages over conventional silicon wafers. In IC technology, the switching speed of circuits fabricated on SOI is increased by 20-50{\%} compared to circuits fabricated on a bulk Si wafer. The required operation voltage is lower in ICs on SOI than in ICs on a bulk silicon wafer, which decreases power consumption and chip heating. In the MEMS industry, the buried oxide layer works as a good sacrificial layer during release etching of diaphragms, beams etc. and offers an excellent etch stop layer for silicon etching. Direct wafer bonding can also be used in the fabrication of more complex structures than SOI. The wafers to be bonded can be of different materials, can contain patterns, and may have multiple layers or ready-made devices. This thesis reports on studies of direct wafer bonding and its use in various applications. Different bonding processes used in microelectronics are briefly described. The main focus of this thesis is on the plasma activation-based low temperature bonding process, and on the control of bond strength by surface preparation. A novel method for bond strength measurement is introduced. This method, based on buried oxide etching, is presented and compared with other methods used in evaluating bond quality. This thesis also contains results on research of different applications requiring direct wafer bonding. Heterogeneous integration, pre-processed SOI fabrication, and wafer scale packaging are the main application topics.",
keywords = "direct wafer bonding, MEMS, microelectronics, microelectromechanical systems, SOI, silicon-on-insulator, integrated circuits, bond strength measurement, heterogeneous integration, pre-processed SOI fabrication, wafer-scale packaging, plasma activation",
author = "Tommi Suni",
year = "2006",
language = "English",
isbn = "951-38-6851-6",
series = "VTT Publications",
publisher = "VTT Technical Research Centre of Finland",
number = "609",
address = "Finland",
school = "Aalto University",

}

Suni, T 2006, 'Direct wafer bonding for MEMS and microelectronics: Dissertation', Doctor Degree, Aalto University, Espoo.

Direct wafer bonding for MEMS and microelectronics : Dissertation. / Suni, Tommi.

Espoo : VTT Technical Research Centre of Finland, 2006. 140 p.

Research output: ThesisDissertation

TY - THES

T1 - Direct wafer bonding for MEMS and microelectronics

T2 - Dissertation

AU - Suni, Tommi

PY - 2006

Y1 - 2006

N2 - Direct wafer bonding is a method for fabricating advanced substrates for microelectromechanical systems (MEMS) and integrated circuits (IC). The most typical example of such an advanced substrate is the silicon-on-insulator (SOI) wafer. SOI wafers offer many advantages over conventional silicon wafers. In IC technology, the switching speed of circuits fabricated on SOI is increased by 20-50% compared to circuits fabricated on a bulk Si wafer. The required operation voltage is lower in ICs on SOI than in ICs on a bulk silicon wafer, which decreases power consumption and chip heating. In the MEMS industry, the buried oxide layer works as a good sacrificial layer during release etching of diaphragms, beams etc. and offers an excellent etch stop layer for silicon etching. Direct wafer bonding can also be used in the fabrication of more complex structures than SOI. The wafers to be bonded can be of different materials, can contain patterns, and may have multiple layers or ready-made devices. This thesis reports on studies of direct wafer bonding and its use in various applications. Different bonding processes used in microelectronics are briefly described. The main focus of this thesis is on the plasma activation-based low temperature bonding process, and on the control of bond strength by surface preparation. A novel method for bond strength measurement is introduced. This method, based on buried oxide etching, is presented and compared with other methods used in evaluating bond quality. This thesis also contains results on research of different applications requiring direct wafer bonding. Heterogeneous integration, pre-processed SOI fabrication, and wafer scale packaging are the main application topics.

AB - Direct wafer bonding is a method for fabricating advanced substrates for microelectromechanical systems (MEMS) and integrated circuits (IC). The most typical example of such an advanced substrate is the silicon-on-insulator (SOI) wafer. SOI wafers offer many advantages over conventional silicon wafers. In IC technology, the switching speed of circuits fabricated on SOI is increased by 20-50% compared to circuits fabricated on a bulk Si wafer. The required operation voltage is lower in ICs on SOI than in ICs on a bulk silicon wafer, which decreases power consumption and chip heating. In the MEMS industry, the buried oxide layer works as a good sacrificial layer during release etching of diaphragms, beams etc. and offers an excellent etch stop layer for silicon etching. Direct wafer bonding can also be used in the fabrication of more complex structures than SOI. The wafers to be bonded can be of different materials, can contain patterns, and may have multiple layers or ready-made devices. This thesis reports on studies of direct wafer bonding and its use in various applications. Different bonding processes used in microelectronics are briefly described. The main focus of this thesis is on the plasma activation-based low temperature bonding process, and on the control of bond strength by surface preparation. A novel method for bond strength measurement is introduced. This method, based on buried oxide etching, is presented and compared with other methods used in evaluating bond quality. This thesis also contains results on research of different applications requiring direct wafer bonding. Heterogeneous integration, pre-processed SOI fabrication, and wafer scale packaging are the main application topics.

KW - direct wafer bonding

KW - MEMS

KW - microelectronics

KW - microelectromechanical systems

KW - SOI

KW - silicon-on-insulator

KW - integrated circuits

KW - bond strength measurement

KW - heterogeneous integration

KW - pre-processed SOI fabrication

KW - wafer-scale packaging

KW - plasma activation

M3 - Dissertation

SN - 951-38-6851-6

T3 - VTT Publications

PB - VTT Technical Research Centre of Finland

CY - Espoo

ER -

Suni T. Direct wafer bonding for MEMS and microelectronics: Dissertation. Espoo: VTT Technical Research Centre of Finland, 2006. 140 p.