Abstract
In this paper the design and implementation of a delay-locked loop based temperature compensated MEMS clock is presented.
The system is providing a temperature compensated 48 MHz clock signal for the range of - 40 to 85°C.
The temperature compensation is achieved by a combination of initial and an autonomous background calibration.
The main design guidelines have been on high integration level and minimum silicon area while maintaining a low timing jitter and power consumption.
The design was implemented by utilizing Austria Micro Systems (AMS) 0.35 μm standard CMOS process technology.
The implementation occupies 1.75 mm 2 of silicon area.
The system is providing a temperature compensated 48 MHz clock signal for the range of - 40 to 85°C.
The temperature compensation is achieved by a combination of initial and an autonomous background calibration.
The main design guidelines have been on high integration level and minimum silicon area while maintaining a low timing jitter and power consumption.
The design was implemented by utilizing Austria Micro Systems (AMS) 0.35 μm standard CMOS process technology.
The implementation occupies 1.75 mm 2 of silicon area.
| Original language | English |
|---|---|
| Title of host publication | Proceedings |
| Subtitle of host publication | 28th Norchip Conference, NORCHIP 2010 |
| Place of Publication | Piscataway, NJ, USA |
| Publisher | IEEE Institute of Electrical and Electronic Engineers |
| Number of pages | 4 |
| ISBN (Electronic) | 978-1-4244-8973-2 |
| ISBN (Print) | 978-1-4244-8972-5 |
| DOIs | |
| Publication status | Published - 2010 |
| MoE publication type | A4 Article in a conference publication |
| Event | 28th Norchip Conference, NORCHIP 2010 - Tampere, Finland Duration: 15 Nov 2010 → 16 Nov 2010 |
Conference
| Conference | 28th Norchip Conference, NORCHIP 2010 |
|---|---|
| Abbreviated title | NORCHIP 2010 |
| Country/Territory | Finland |
| City | Tampere |
| Period | 15/11/10 → 16/11/10 |