DSNOC: A hybrid dense-sparse network-on-chip architecture for efficient scalable computing

T.C. Xu, V. Leppänen, Martti Forsell

Research output: Chapter in Book/Report/Conference proceedingConference article in proceedingsScientificpeer-review

4 Citations (Scopus)

Abstract

In this paper, we propose a novel hybrid Dense-Sparse Network-on-Chip (DSNOC) design that takes advantage of both dense and sparse networks. The NoC paradigm is introduced to solve the communication bottleneck and improve system scalability for multicore processors with hundreds or even thousands of cores. Dense mesh network has been used widely in NoCs due to the simplicity of the design and implementation. However the scalability of dense network can be a bottleneck in systems with high traffic volume. Sparse network has been proposed to provide higher bandwidth and better scalability than the dense network, while the size of the interconnection system becomes impractical for large systems. By combining the benefits of both networks, system performance and efficiency can be improved with a proper hybrid design. We analyse and investigate router utilization and traffic distribution of typical mesh networks. The hybrid solution is explored with theoretical analysis and implementation considerations. Experiments are performed by using a full system simulation environment. The evaluation results show that, compared with the dense network, the average network latency and energy delay product of DSNOC are improved by 10.3% and 33% respectively
Original languageEnglish
Title of host publicationProceedings
Subtitle of host publication11th IEEE International Conference on Dependable, Autonomic and Secure Computing, DASC 2013
EditorsXingang Liu, Laurence T. Yang, Chao Sun, Kai Kang
PublisherInstitute of Electrical and Electronic Engineers IEEE
Pages528-535
ISBN (Electronic)978-1-4799-3380-8
ISBN (Print)978-1-4799-3381-5
DOIs
Publication statusPublished - 2013
MoE publication typeA4 Article in a conference publication
Event11th IEEE International Conference on Dependable, Autonomic and Secure Computing, DASC 2013 - Chengdu, Sichuan, China
Duration: 21 Dec 201322 Dec 2013

Conference

Conference11th IEEE International Conference on Dependable, Autonomic and Secure Computing, DASC 2013
Abbreviated titleDASC 2013
CountryChina
CityChengdu, Sichuan
Period21/12/1322/12/13

Fingerprint

Scalability
Routers
Bandwidth
Communication
Network-on-chip
Experiments

Keywords

  • multi-core
  • network-on-chip
  • parallel systems
  • scalable computing
  • sparse networks

Cite this

Xu, T. C., Leppänen, V., & Forsell, M. (2013). DSNOC: A hybrid dense-sparse network-on-chip architecture for efficient scalable computing. In X. Liu, L. T. Yang, C. Sun, & K. Kang (Eds.), Proceedings: 11th IEEE International Conference on Dependable, Autonomic and Secure Computing, DASC 2013 (pp. 528-535). Institute of Electrical and Electronic Engineers IEEE. https://doi.org/10.1109/DASC.2013.119
Xu, T.C. ; Leppänen, V. ; Forsell, Martti. / DSNOC : A hybrid dense-sparse network-on-chip architecture for efficient scalable computing. Proceedings: 11th IEEE International Conference on Dependable, Autonomic and Secure Computing, DASC 2013. editor / Xingang Liu ; Laurence T. Yang ; Chao Sun ; Kai Kang. Institute of Electrical and Electronic Engineers IEEE, 2013. pp. 528-535
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title = "DSNOC: A hybrid dense-sparse network-on-chip architecture for efficient scalable computing",
abstract = "In this paper, we propose a novel hybrid Dense-Sparse Network-on-Chip (DSNOC) design that takes advantage of both dense and sparse networks. The NoC paradigm is introduced to solve the communication bottleneck and improve system scalability for multicore processors with hundreds or even thousands of cores. Dense mesh network has been used widely in NoCs due to the simplicity of the design and implementation. However the scalability of dense network can be a bottleneck in systems with high traffic volume. Sparse network has been proposed to provide higher bandwidth and better scalability than the dense network, while the size of the interconnection system becomes impractical for large systems. By combining the benefits of both networks, system performance and efficiency can be improved with a proper hybrid design. We analyse and investigate router utilization and traffic distribution of typical mesh networks. The hybrid solution is explored with theoretical analysis and implementation considerations. Experiments are performed by using a full system simulation environment. The evaluation results show that, compared with the dense network, the average network latency and energy delay product of DSNOC are improved by 10.3{\%} and 33{\%} respectively",
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Xu, TC, Leppänen, V & Forsell, M 2013, DSNOC: A hybrid dense-sparse network-on-chip architecture for efficient scalable computing. in X Liu, LT Yang, C Sun & K Kang (eds), Proceedings: 11th IEEE International Conference on Dependable, Autonomic and Secure Computing, DASC 2013. Institute of Electrical and Electronic Engineers IEEE, pp. 528-535, 11th IEEE International Conference on Dependable, Autonomic and Secure Computing, DASC 2013, Chengdu, Sichuan, China, 21/12/13. https://doi.org/10.1109/DASC.2013.119

DSNOC : A hybrid dense-sparse network-on-chip architecture for efficient scalable computing. / Xu, T.C.; Leppänen, V.; Forsell, Martti.

Proceedings: 11th IEEE International Conference on Dependable, Autonomic and Secure Computing, DASC 2013. ed. / Xingang Liu; Laurence T. Yang; Chao Sun; Kai Kang. Institute of Electrical and Electronic Engineers IEEE, 2013. p. 528-535.

Research output: Chapter in Book/Report/Conference proceedingConference article in proceedingsScientificpeer-review

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N2 - In this paper, we propose a novel hybrid Dense-Sparse Network-on-Chip (DSNOC) design that takes advantage of both dense and sparse networks. The NoC paradigm is introduced to solve the communication bottleneck and improve system scalability for multicore processors with hundreds or even thousands of cores. Dense mesh network has been used widely in NoCs due to the simplicity of the design and implementation. However the scalability of dense network can be a bottleneck in systems with high traffic volume. Sparse network has been proposed to provide higher bandwidth and better scalability than the dense network, while the size of the interconnection system becomes impractical for large systems. By combining the benefits of both networks, system performance and efficiency can be improved with a proper hybrid design. We analyse and investigate router utilization and traffic distribution of typical mesh networks. The hybrid solution is explored with theoretical analysis and implementation considerations. Experiments are performed by using a full system simulation environment. The evaluation results show that, compared with the dense network, the average network latency and energy delay product of DSNOC are improved by 10.3% and 33% respectively

AB - In this paper, we propose a novel hybrid Dense-Sparse Network-on-Chip (DSNOC) design that takes advantage of both dense and sparse networks. The NoC paradigm is introduced to solve the communication bottleneck and improve system scalability for multicore processors with hundreds or even thousands of cores. Dense mesh network has been used widely in NoCs due to the simplicity of the design and implementation. However the scalability of dense network can be a bottleneck in systems with high traffic volume. Sparse network has been proposed to provide higher bandwidth and better scalability than the dense network, while the size of the interconnection system becomes impractical for large systems. By combining the benefits of both networks, system performance and efficiency can be improved with a proper hybrid design. We analyse and investigate router utilization and traffic distribution of typical mesh networks. The hybrid solution is explored with theoretical analysis and implementation considerations. Experiments are performed by using a full system simulation environment. The evaluation results show that, compared with the dense network, the average network latency and energy delay product of DSNOC are improved by 10.3% and 33% respectively

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Xu TC, Leppänen V, Forsell M. DSNOC: A hybrid dense-sparse network-on-chip architecture for efficient scalable computing. In Liu X, Yang LT, Sun C, Kang K, editors, Proceedings: 11th IEEE International Conference on Dependable, Autonomic and Secure Computing, DASC 2013. Institute of Electrical and Electronic Engineers IEEE. 2013. p. 528-535 https://doi.org/10.1109/DASC.2013.119