Abstract
As systems on chip are evolving to networks on chip (NOC), providing a unified communication infrastructure for a number of computational resources, being able to easily implement computational tasks as a parallel program, that can be efficiently executed by multiple resources together, is becoming increasingly important. Recent advances in thread-level parallel (TLP) architectures have made it possible to implement efficiently an easy-to-use synchronous shared memory programming model (Parallel Random Access Machine, PRAM) on a NOC. On our previous work we have introduced e, a fine-grained TLP programming language for synchronous shared memory NOC architectures realizing the PRAM model. The language uses a familiar c-like syntax and provides support for shared and private variables, arbitrary hierarchical groups of threads, and synchronous control structures. This allows a programmer to use various advanced TLP programming techniques like data parallelism, divide-and-conquer technique, different blocking techniques, and both synchronous and asynchronous programming style. In this paper we describe ec, an experimental compiler for e. We will also shortly evaluate the e-compiler with real parallel programs using our scalable Eclipse NOC architecture.
Original language | English |
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Title of host publication | 2004 International Symposium on System-on-Chip Proceedings |
Publisher | IEEE Institute of Electrical and Electronic Engineers |
Pages | 157-160 |
ISBN (Print) | 978-0-7803-8558-0 |
DOIs | |
Publication status | Published - 2004 |
MoE publication type | A4 Article in a conference publication |
Event | 2004 International Symposium on System-on-Chip - Tampere, Finland Duration: 16 Nov 2004 → 18 Nov 2004 |
Conference
Conference | 2004 International Symposium on System-on-Chip |
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Country/Territory | Finland |
City | Tampere |
Period | 16/11/04 → 18/11/04 |