Efficient barrier synchronization mechanism for emulated shared memory NOCs

Martti Forsell

doi:10.1109/ISSOC.2004.1411139

Efficient barrier synchronization mechanism for emulated shared memory NOCs

Martti Forsell

Research output: Chapter in Book/Report/Conference proceeding › Conference article in proceedings › Scientific › peer-review

3 Citations (Scopus)

Abstract

Explicit synchronization mechanisms capable of arbitrary simultaneous barriers are needed to support parallely recursive synchronous MIMD programming even in step synchronous emulated shared memory machine (ESMM) because control of threads may privately depend on input values. Current synchronization mechanisms fail to support arbitrary simultaneous barriers or are not scalable with future silicon technologies. In this paper we propose a novel constant execution time barrier synchronization mechanism for scalable ESMMs using active memory. The mechanism is applied to our Eclipse network-on-chip architecture and evaluated briefly.

Original language	English
Title of host publication	2004 International Symposium on System-on-Chip Proceedings
Publisher	IEEE Institute of Electrical and Electronic Engineers
Pages	33-36
ISBN (Print)	978-0-7803-8558-0
DOIs	https://doi.org/10.1109/ISSOC.2004.1411139
Publication status	Published - 2004
MoE publication type	A4 Article in a conference publication
Event	2004 International Symposium on System-on-Chip - Tampere, Finland Duration: 16 Nov 2004 → 18 Nov 2004

Conference

Conference	2004 International Symposium on System-on-Chip
Country/Territory	Finland
City	Tampere
Period	16/11/04 → 18/11/04

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10.1109/ISSOC.2004.1411139

Cite this

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title = "Efficient barrier synchronization mechanism for emulated shared memory NOCs",

abstract = "Explicit synchronization mechanisms capable of arbitrary simultaneous barriers are needed to support parallely recursive synchronous MIMD programming even in step synchronous emulated shared memory machine (ESMM) because control of threads may privately depend on input values. Current synchronization mechanisms fail to support arbitrary simultaneous barriers or are not scalable with future silicon technologies. In this paper we propose a novel constant execution time barrier synchronization mechanism for scalable ESMMs using active memory. The mechanism is applied to our Eclipse network-on-chip architecture and evaluated briefly.",

author = "Martti Forsell",

year = "2004",

doi = "10.1109/ISSOC.2004.1411139",

language = "English",

isbn = "978-0-7803-8558-0",

pages = "33--36",

booktitle = "2004 International Symposium on System-on-Chip Proceedings",

publisher = "IEEE Institute of Electrical and Electronic Engineers",

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note = "2004 International Symposium on System-on-Chip ; Conference date: 16-11-2004 Through 18-11-2004",

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T1 - Efficient barrier synchronization mechanism for emulated shared memory NOCs

AU - Forsell, Martti

PY - 2004

Y1 - 2004

N2 - Explicit synchronization mechanisms capable of arbitrary simultaneous barriers are needed to support parallely recursive synchronous MIMD programming even in step synchronous emulated shared memory machine (ESMM) because control of threads may privately depend on input values. Current synchronization mechanisms fail to support arbitrary simultaneous barriers or are not scalable with future silicon technologies. In this paper we propose a novel constant execution time barrier synchronization mechanism for scalable ESMMs using active memory. The mechanism is applied to our Eclipse network-on-chip architecture and evaluated briefly.

AB - Explicit synchronization mechanisms capable of arbitrary simultaneous barriers are needed to support parallely recursive synchronous MIMD programming even in step synchronous emulated shared memory machine (ESMM) because control of threads may privately depend on input values. Current synchronization mechanisms fail to support arbitrary simultaneous barriers or are not scalable with future silicon technologies. In this paper we propose a novel constant execution time barrier synchronization mechanism for scalable ESMMs using active memory. The mechanism is applied to our Eclipse network-on-chip architecture and evaluated briefly.

U2 - 10.1109/ISSOC.2004.1411139

DO - 10.1109/ISSOC.2004.1411139

M3 - Conference article in proceedings

SN - 978-0-7803-8558-0

SP - 33

EP - 36

BT - 2004 International Symposium on System-on-Chip Proceedings

PB - IEEE Institute of Electrical and Electronic Engineers

T2 - 2004 International Symposium on System-on-Chip

Y2 - 16 November 2004 through 18 November 2004

ER -

Efficient barrier synchronization mechanism for emulated shared memory NOCs

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