Electron mobility and magneto transport study of ultra-thin channel double-gate Si MOSFETs

Mika Prunnila (Corresponding Author), Jouni Ahopelto, F. Gamiz

    Research output: Contribution to journalArticleScientificpeer-review

    6 Citations (Scopus)


    We report on detailed room temperature and low temperature transport properties of double-gate Si MOSFETs with the Si well thickness in the range ∼7–17 nm. The devices were fabricated on silicon-on-insulator wafers utilizing wafer bonding, which enabled us to use heavily doped metallic back gate. We observe mobility enhancement effects at symmetric gate bias at room temperature, which is the finger print of the volume inversion/accumulation effect. An asymmetry in the mobility is detected at 300 K and at 1.6 K between the top and back interfaces of the Si well, which is interpreted to arise from different surface roughnesses of the interfaces. Low temperature peak mobilities of the reported devices scale monotonically with Si well thickness and the maximum low temperature mobility was 1.9 m2/V s, which was measured from a 16.5 nm thick device. In the magneto transport data we observe single and two sub-band Landau level filling factor behavior depending on the well thickness and gate biasing.

    Original languageEnglish
    Pages (from-to)1516 - 1521
    Number of pages6
    JournalSolid-State Electronics
    Issue number9
    Publication statusPublished - 2005
    MoE publication typeA1 Journal article-refereed


    • quantum wells
    • silicon-on-insulator
    • SOI
    • quantum hall
    • electron transport
    • MOSFET


    Dive into the research topics of 'Electron mobility and magneto transport study of ultra-thin channel double-gate Si MOSFETs'. Together they form a unique fingerprint.

    Cite this