Electron mobility and magneto transport study of ultra-thin channel double-gate Si MOSFETs

Mika Prunnila (Corresponding Author), Jouni Ahopelto, F. Gamiz

Research output: Contribution to journalArticleScientificpeer-review

6 Citations (Scopus)

Abstract

We report on detailed room temperature and low temperature transport properties of double-gate Si MOSFETs with the Si well thickness in the range ∼7–17 nm. The devices were fabricated on silicon-on-insulator wafers utilizing wafer bonding, which enabled us to use heavily doped metallic back gate. We observe mobility enhancement effects at symmetric gate bias at room temperature, which is the finger print of the volume inversion/accumulation effect. An asymmetry in the mobility is detected at 300 K and at 1.6 K between the top and back interfaces of the Si well, which is interpreted to arise from different surface roughnesses of the interfaces. Low temperature peak mobilities of the reported devices scale monotonically with Si well thickness and the maximum low temperature mobility was 1.9 m2/V s, which was measured from a 16.5 nm thick device. In the magneto transport data we observe single and two sub-band Landau level filling factor behavior depending on the well thickness and gate biasing.

Original languageEnglish
Pages (from-to)1516 - 1521
Number of pages6
JournalSolid-State Electronics
Volume49
Issue number9
DOIs
Publication statusPublished - 2005
MoE publication typeA1 Journal article-refereed

Fingerprint

Electron mobility
electron mobility
field effect transistors
wafers
Temperature
room temperature
Wafer bonding
Silicon
surface roughness
transport properties
Transport properties
asymmetry
insulators
inversions
Surface roughness
augmentation
silicon
temperature

Keywords

  • quantum wells
  • silicon-on-insulator
  • SOI
  • quantum hall
  • electron transport
  • MOSFET

Cite this

@article{42729362e52f4c3599420077aa048f80,
title = "Electron mobility and magneto transport study of ultra-thin channel double-gate Si MOSFETs",
abstract = "We report on detailed room temperature and low temperature transport properties of double-gate Si MOSFETs with the Si well thickness in the range ∼7–17 nm. The devices were fabricated on silicon-on-insulator wafers utilizing wafer bonding, which enabled us to use heavily doped metallic back gate. We observe mobility enhancement effects at symmetric gate bias at room temperature, which is the finger print of the volume inversion/accumulation effect. An asymmetry in the mobility is detected at 300 K and at 1.6 K between the top and back interfaces of the Si well, which is interpreted to arise from different surface roughnesses of the interfaces. Low temperature peak mobilities of the reported devices scale monotonically with Si well thickness and the maximum low temperature mobility was 1.9 m2/V s, which was measured from a 16.5 nm thick device. In the magneto transport data we observe single and two sub-band Landau level filling factor behavior depending on the well thickness and gate biasing.",
keywords = "quantum wells, silicon-on-insulator, SOI, quantum hall, electron transport, MOSFET",
author = "Mika Prunnila and Jouni Ahopelto and F. Gamiz",
year = "2005",
doi = "10.1016/j.sse.2005.07.016",
language = "English",
volume = "49",
pages = "1516 -- 1521",
journal = "Solid-State Electronics",
issn = "0038-1101",
publisher = "Elsevier",
number = "9",

}

Electron mobility and magneto transport study of ultra-thin channel double-gate Si MOSFETs. / Prunnila, Mika (Corresponding Author); Ahopelto, Jouni; Gamiz, F.

In: Solid-State Electronics, Vol. 49, No. 9, 2005, p. 1516 - 1521.

Research output: Contribution to journalArticleScientificpeer-review

TY - JOUR

T1 - Electron mobility and magneto transport study of ultra-thin channel double-gate Si MOSFETs

AU - Prunnila, Mika

AU - Ahopelto, Jouni

AU - Gamiz, F.

PY - 2005

Y1 - 2005

N2 - We report on detailed room temperature and low temperature transport properties of double-gate Si MOSFETs with the Si well thickness in the range ∼7–17 nm. The devices were fabricated on silicon-on-insulator wafers utilizing wafer bonding, which enabled us to use heavily doped metallic back gate. We observe mobility enhancement effects at symmetric gate bias at room temperature, which is the finger print of the volume inversion/accumulation effect. An asymmetry in the mobility is detected at 300 K and at 1.6 K between the top and back interfaces of the Si well, which is interpreted to arise from different surface roughnesses of the interfaces. Low temperature peak mobilities of the reported devices scale monotonically with Si well thickness and the maximum low temperature mobility was 1.9 m2/V s, which was measured from a 16.5 nm thick device. In the magneto transport data we observe single and two sub-band Landau level filling factor behavior depending on the well thickness and gate biasing.

AB - We report on detailed room temperature and low temperature transport properties of double-gate Si MOSFETs with the Si well thickness in the range ∼7–17 nm. The devices were fabricated on silicon-on-insulator wafers utilizing wafer bonding, which enabled us to use heavily doped metallic back gate. We observe mobility enhancement effects at symmetric gate bias at room temperature, which is the finger print of the volume inversion/accumulation effect. An asymmetry in the mobility is detected at 300 K and at 1.6 K between the top and back interfaces of the Si well, which is interpreted to arise from different surface roughnesses of the interfaces. Low temperature peak mobilities of the reported devices scale monotonically with Si well thickness and the maximum low temperature mobility was 1.9 m2/V s, which was measured from a 16.5 nm thick device. In the magneto transport data we observe single and two sub-band Landau level filling factor behavior depending on the well thickness and gate biasing.

KW - quantum wells

KW - silicon-on-insulator

KW - SOI

KW - quantum hall

KW - electron transport

KW - MOSFET

U2 - 10.1016/j.sse.2005.07.016

DO - 10.1016/j.sse.2005.07.016

M3 - Article

VL - 49

SP - 1516

EP - 1521

JO - Solid-State Electronics

JF - Solid-State Electronics

SN - 0038-1101

IS - 9

ER -