Flip chip mounting of bare dice is gaining widespread use in microelectronics packaging. The main drivers for this technology are high packaging density, improved performance at high frequency, low parasitic effects and potentially high reliability and low cost. Many companies have made significant efforts to develop a technology for bump processing, bare die testing and underfill encapsulation to gain the benefit of all potential advantages. We have focussed on low cost bumping of fully processed silicon wafers to develop a flexible scheme for various reflow requirements. The bumping process is based on galvanic plating from an alloy solution or, alternatively, from several elemental plating baths. Sputtered Mo/Cu or Cr/Cu is used as a wettable base for electroplating. Excess base metal is removed by using the bumps as an etching mask. Variation of the alloy composition or the layer structure, allows the adjustment of the bump reflow temperature for the specific requirements of the assembly. Using binary tin-lead and ternary tin-lead-bismuth alloys, reflow temperatures from 100 °C (bismuth rich alloys) to above 300 °C (lead rich alloys) can be covered. The influence of the plating current density on the final alloy composition has been established by ion beam analysis of the plated layers and a series of reflow experiments. To control the plating uniformity and the alloy composition, a new cup plating system has been built with a random flow pattern and continuous adjustment of the current density. A well-controlled reflow of the bumps has been achieved in hot glycerol up to the eutectic point of tin-lead alloys. For high temperature alloys, high molecular weight organic liquids have been used. A tensile pull strength of 20 g per bump and resistance of 5 mΩ per bump have been measured for typical eutectic tin-lead bumps of 100 μm in diameter.
|Physica Scripta: Topical Issues
|17th Nordic Semiconductor Meeting 17NSM
|17/06/96 → 20/06/96