Abstract
In the context of fast adoption and deployment of recent video compression standard and thanks to recent high performance embedded processors, software video decoding can be performed in real time. But, it becomes among the most energy-intensive applications. Current embedded processors are based on multi-core architecture with advanced convenient features such as Dynamic Voltage Frequency Scaling (DVFS) in order to reduce their power consumption, allowing low power video decoding when no hardware decoding support is available for a given device. This paper deals with energy efficiency impact of different parallelization strategies of a software High Efficiency Video Coding (HEVC) decoder on multi-core ARM big.LITTLE processor. These strategies include the exploitation of data and task-level parallelism, as well as the use of different available DVFS policies.
Original language | English |
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Title of host publication | CF '15 Proceedings of the 12th ACM International Conference on Computing Frontiers |
Publisher | Association for Computing Machinery ACM |
ISBN (Print) | 978-1-4503-3358-0 |
DOIs | |
Publication status | Published - 2015 |
MoE publication type | A4 Article in a conference publication |
Event | 12th ACM International Conference on Computing Frontiers, CF 2016 - Ischia, Italy Duration: 18 May 2015 → 21 May 2015 Conference number: 12 |
Conference
Conference | 12th ACM International Conference on Computing Frontiers, CF 2016 |
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Abbreviated title | CF 2016 |
Country/Territory | Italy |
City | Ischia |
Period | 18/05/15 → 21/05/15 |
Keywords
- DVFS
- embedded systems
- framebased parallelism
- H.265
- HEVC
- low power
- SIMD
- video decoder
- WPP