Energy efficiency of a parallel HEVC software decoder for embedded devices

Erwan Raffin, Wassim Hamidouche, Erwan Nogues, Maxime Pelcat, Daniel Menard, Seppo Tomperi

Research output: Chapter in Book/Report/Conference proceedingConference article in proceedingsScientificpeer-review

2 Citations (Scopus)


In the context of fast adoption and deployment of recent video compression standard and thanks to recent high performance embedded processors, software video decoding can be performed in real time. But, it becomes among the most energy-intensive applications. Current embedded processors are based on multi-core architecture with advanced convenient features such as Dynamic Voltage Frequency Scaling (DVFS) in order to reduce their power consumption, allowing low power video decoding when no hardware decoding support is available for a given device. This paper deals with energy efficiency impact of different parallelization strategies of a software High Efficiency Video Coding (HEVC) decoder on multi-core ARM big.LITTLE processor. These strategies include the exploitation of data and task-level parallelism, as well as the use of different available DVFS policies.
Original languageEnglish
Title of host publicationCF '15 Proceedings of the 12th ACM International Conference on Computing Frontiers
PublisherAssociation for Computing Machinery ACM
ISBN (Print)978-1-4503-3358-0
Publication statusPublished - 2015
MoE publication typeA4 Article in a conference publication
Event12th ACM International Conference on Computing Frontiers, CF 2016 - Ischia, Italy
Duration: 18 May 201521 May 2015
Conference number: 12


Conference12th ACM International Conference on Computing Frontiers, CF 2016
Abbreviated titleCF 2016


  • DVFS
  • embedded systems
  • framebased parallelism
  • H.265
  • HEVC
  • low power
  • SIMD
  • video decoder
  • WPP


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