Estimates for the partial capasitance of a printed circuit board via

Johan C.-E. Sten, Tommi Dufva

Research output: Contribution to journalArticleScientificpeer-review

4 Citations (Scopus)

Abstract

A printed circuit board via is analyzed as a collection of sections bounded by grounded planes. A semianalytical expression for the capacitance of such a section is deduced and numerically adapted to solutions obtained with the finite‐element method. For high permittivities, one may also estimate the capacitance of a via terminating at a dielectric interface.
Original languageEnglish
Pages (from-to)160 - 163
Number of pages4
JournalMicrowave and Optical Technology Letters
Volume20
Issue number3
DOIs
Publication statusPublished - 1999
MoE publication typeA1 Journal article-refereed

Fingerprint

printed circuits
circuit boards
Printed circuit boards
Capacitance
capacitance
estimates
stopping
Permittivity
permittivity

Keywords

  • interconnects
  • circuit board via
  • packaging

Cite this

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Estimates for the partial capasitance of a printed circuit board via. / Sten, Johan C.-E.; Dufva, Tommi.

In: Microwave and Optical Technology Letters, Vol. 20, No. 3, 1999, p. 160 - 163.

Research output: Contribution to journalArticleScientificpeer-review

TY - JOUR

T1 - Estimates for the partial capasitance of a printed circuit board via

AU - Sten, Johan C.-E.

AU - Dufva, Tommi

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N2 - A printed circuit board via is analyzed as a collection of sections bounded by grounded planes. A semianalytical expression for the capacitance of such a section is deduced and numerically adapted to solutions obtained with the finite‐element method. For high permittivities, one may also estimate the capacitance of a via terminating at a dielectric interface.

AB - A printed circuit board via is analyzed as a collection of sections bounded by grounded planes. A semianalytical expression for the capacitance of such a section is deduced and numerically adapted to solutions obtained with the finite‐element method. For high permittivities, one may also estimate the capacitance of a via terminating at a dielectric interface.

KW - interconnects

KW - circuit board via

KW - packaging

U2 - 10.1002/(SICI)1098-2760(19990205)20:3<160::AID-MOP3>3.0.CO;2-E

DO - 10.1002/(SICI)1098-2760(19990205)20:3<160::AID-MOP3>3.0.CO;2-E

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JO - Microwave and Optical Technology Letters

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