Abstract
A printed circuit board via is analyzed as a collection of sections
bounded by grounded planes. A semianalytical expression for the
capacitance of such a section is deduced and numerically adapted to
solutions obtained with the finite‐element method. For high
permittivities, one may also estimate the capacitance of a via
terminating at a dielectric interface.
| Original language | English |
|---|---|
| Pages (from-to) | 160 - 163 |
| Number of pages | 4 |
| Journal | Microwave and Optical Technology Letters |
| Volume | 20 |
| Issue number | 3 |
| DOIs | |
| Publication status | Published - 1999 |
| MoE publication type | A1 Journal article-refereed |
Keywords
- interconnects
- circuit board via
- packaging