Estimating the utilization of embedded FPGA co-processor

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    7 Citations (Scopus)

    Abstract

    Embedded FPGA co-processors will bring new alternatives for SoC system designers. Comparison of software implementations and reconfigurable hardware implementations will need fast and easy-to-use estimation techniques. In this paper, we present an estimation approach for the resource utilization of the embedded FPGA co-processor. Our approach is based on the principles of high-level synthesis, such as force-directed scheduling, resource allocation, operation assignment and interconnection binding. The method has been applied to simple test cases and a C-language model of MPEG-2 decoder. The average hardware estimation error of MPEG-2 functions was 25%.
    Original languageEnglish
    Title of host publicationProceedings: Euromicro Symposium on Digital Systems Design 2003
    PublisherIEEE Institute of Electrical and Electronic Engineers
    Pages214-221
    ISBN (Print)0-7695-2003-0
    DOIs
    Publication statusPublished - 2003
    MoE publication typeA4 Article in a conference publication
    EventEuromicro Symposium on Digital System Design, DSD 2003: Architectures, Methods and Tools - Antalaya, Turkey
    Duration: 3 Sep 20035 Sep 2003

    Conference

    ConferenceEuromicro Symposium on Digital System Design, DSD 2003
    CountryTurkey
    CityAntalaya
    Period3/09/035/09/03

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  • Cite this

    Qu, Y., & Soininen, J-P. (2003). Estimating the utilization of embedded FPGA co-processor. In Proceedings: Euromicro Symposium on Digital Systems Design 2003 (pp. 214-221). IEEE Institute of Electrical and Electronic Engineers. https://doi.org/10.1109/DSD.2003.1231929