Estimating the utilization of embedded FPGA co-processor

    Research output: Chapter in Book/Report/Conference proceedingConference article in proceedingsScientificpeer-review

    8 Citations (Scopus)


    Embedded FPGA co-processors will bring new alternatives for SoC system designers. Comparison of software implementations and reconfigurable hardware implementations will need fast and easy-to-use estimation techniques. In this paper, we present an estimation approach for the resource utilization of the embedded FPGA co-processor. Our approach is based on the principles of high-level synthesis, such as force-directed scheduling, resource allocation, operation assignment and interconnection binding. The method has been applied to simple test cases and a C-language model of MPEG-2 decoder. The average hardware estimation error of MPEG-2 functions was 25%.
    Original languageEnglish
    Title of host publicationProceedings: Euromicro Symposium on Digital Systems Design 2003
    PublisherIEEE Institute of Electrical and Electronic Engineers
    ISBN (Print)0-7695-2003-0
    Publication statusPublished - 2003
    MoE publication typeA4 Article in a conference publication
    EventEuromicro Symposium on Digital System Design, DSD 2003: Architectures, Methods and Tools - Antalaya, Turkey
    Duration: 3 Sept 20035 Sept 2003


    ConferenceEuromicro Symposium on Digital System Design, DSD 2003


    Dive into the research topics of 'Estimating the utilization of embedded FPGA co-processor'. Together they form a unique fingerprint.

    Cite this