Estimation apporach supporting HW/SW partitioning decisions for reconfigurable System-on-Chip

Master's thesis

Yang Qu

Research output: ThesisMaster's thesisTheses

Abstract

Current technology has enabled us to include general-purpose processors, fixed hardware accelerators and reconfigurable logic units into a SoC. Designers will face more problems of how to make appropriate HW/SW partitioning decisions because of the lack of proper supporting facilities. This thesis presents an estimation approach to supporting HW/SW partitioning decisions for SoC consisting of a general-purpose processor and an embedded Field Programmable Gate Array (eFPGA). The estimation approach consists of a high-level synthesis-based HW estimator and a mappability-based SW estimator. It can produce the following information: HW resource utilization, feasibility of mapping applications onto the targeting general-purpose processor core, and HW/SW speed-up factor. The VCC and the SimpleScalar were used for validating the SW estimator. The average error was about 60%, when comparing the estimation results to the VCC results. For the SimpleScalar results, the SW estimation approach had an accuracy of about +43%. The OCAPI-xl and the Synplify were used in the synthesis-based approach for validating the HW estimator. The results were relatively close to the synthesis results, and the average error was about +25%. The estimation approach has proven its usefulness in HW/SW partitioning especially when timing/area constraints are the main concerns.
Original languageEnglish
QualificationMaster Degree
Awarding Institution
  • University of Oulu
Place of PublicationOulu
Publisher
Publication statusPublished - 2003
MoE publication typeG2 Master's thesis, polytechnic Master's thesis

Fingerprint

Particle accelerators
Field programmable gate arrays (FPGA)
System-on-chip
Hardware
High level synthesis

Cite this

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title = "Estimation apporach supporting HW/SW partitioning decisions for reconfigurable System-on-Chip: Master's thesis",
abstract = "Current technology has enabled us to include general-purpose processors, fixed hardware accelerators and reconfigurable logic units into a SoC. Designers will face more problems of how to make appropriate HW/SW partitioning decisions because of the lack of proper supporting facilities. This thesis presents an estimation approach to supporting HW/SW partitioning decisions for SoC consisting of a general-purpose processor and an embedded Field Programmable Gate Array (eFPGA). The estimation approach consists of a high-level synthesis-based HW estimator and a mappability-based SW estimator. It can produce the following information: HW resource utilization, feasibility of mapping applications onto the targeting general-purpose processor core, and HW/SW speed-up factor. The VCC and the SimpleScalar were used for validating the SW estimator. The average error was about 60{\%}, when comparing the estimation results to the VCC results. For the SimpleScalar results, the SW estimation approach had an accuracy of about +43{\%}. The OCAPI-xl and the Synplify were used in the synthesis-based approach for validating the HW estimator. The results were relatively close to the synthesis results, and the average error was about +25{\%}. The estimation approach has proven its usefulness in HW/SW partitioning especially when timing/area constraints are the main concerns.",
author = "Yang Qu",
note = "CA: ELE OH: pro gradu Oulun yliopisto, s{\"a}hk{\"o}- ja tietotekniikan osasto",
year = "2003",
language = "English",
publisher = "University of Oulu",
address = "Finland",
school = "University of Oulu",

}

Estimation apporach supporting HW/SW partitioning decisions for reconfigurable System-on-Chip : Master's thesis. / Qu, Yang.

Oulu : University of Oulu, 2003. 76 p.

Research output: ThesisMaster's thesisTheses

TY - THES

T1 - Estimation apporach supporting HW/SW partitioning decisions for reconfigurable System-on-Chip

T2 - Master's thesis

AU - Qu, Yang

N1 - CA: ELE OH: pro gradu Oulun yliopisto, sähkö- ja tietotekniikan osasto

PY - 2003

Y1 - 2003

N2 - Current technology has enabled us to include general-purpose processors, fixed hardware accelerators and reconfigurable logic units into a SoC. Designers will face more problems of how to make appropriate HW/SW partitioning decisions because of the lack of proper supporting facilities. This thesis presents an estimation approach to supporting HW/SW partitioning decisions for SoC consisting of a general-purpose processor and an embedded Field Programmable Gate Array (eFPGA). The estimation approach consists of a high-level synthesis-based HW estimator and a mappability-based SW estimator. It can produce the following information: HW resource utilization, feasibility of mapping applications onto the targeting general-purpose processor core, and HW/SW speed-up factor. The VCC and the SimpleScalar were used for validating the SW estimator. The average error was about 60%, when comparing the estimation results to the VCC results. For the SimpleScalar results, the SW estimation approach had an accuracy of about +43%. The OCAPI-xl and the Synplify were used in the synthesis-based approach for validating the HW estimator. The results were relatively close to the synthesis results, and the average error was about +25%. The estimation approach has proven its usefulness in HW/SW partitioning especially when timing/area constraints are the main concerns.

AB - Current technology has enabled us to include general-purpose processors, fixed hardware accelerators and reconfigurable logic units into a SoC. Designers will face more problems of how to make appropriate HW/SW partitioning decisions because of the lack of proper supporting facilities. This thesis presents an estimation approach to supporting HW/SW partitioning decisions for SoC consisting of a general-purpose processor and an embedded Field Programmable Gate Array (eFPGA). The estimation approach consists of a high-level synthesis-based HW estimator and a mappability-based SW estimator. It can produce the following information: HW resource utilization, feasibility of mapping applications onto the targeting general-purpose processor core, and HW/SW speed-up factor. The VCC and the SimpleScalar were used for validating the SW estimator. The average error was about 60%, when comparing the estimation results to the VCC results. For the SimpleScalar results, the SW estimation approach had an accuracy of about +43%. The OCAPI-xl and the Synplify were used in the synthesis-based approach for validating the HW estimator. The results were relatively close to the synthesis results, and the average error was about +25%. The estimation approach has proven its usefulness in HW/SW partitioning especially when timing/area constraints are the main concerns.

M3 - Master's thesis

PB - University of Oulu

CY - Oulu

ER -