Current technology has enabled us to include general-purpose processors, fixed hardware accelerators and reconfigurable logic units into a SoC. Designers will face more problems of how to make appropriate HW/SW partitioning decisions because of the lack of proper supporting facilities. This thesis presents an estimation approach to supporting HW/SW partitioning decisions for SoC consisting of a general-purpose processor and an embedded Field Programmable Gate Array (eFPGA). The estimation approach consists of a high-level synthesis-based HW estimator and a mappability-based SW estimator. It can produce the following information: HW resource utilization, feasibility of mapping applications onto the targeting general-purpose processor core, and HW/SW speed-up factor. The VCC and the SimpleScalar were used for validating the SW estimator. The average error was about 60%, when comparing the estimation results to the VCC results. For the SimpleScalar results, the SW estimation approach had an accuracy of about +43%. The OCAPI-xl and the Synplify were used in the synthesis-based approach for validating the HW estimator. The results were relatively close to the synthesis results, and the average error was about +25%. The estimation approach has proven its usefulness in HW/SW partitioning especially when timing/area constraints are the main concerns.
|Place of Publication||Oulu|
|Publication status||Published - 2003|
|MoE publication type||G2 Master's thesis, polytechnic Master's thesis|