Estimation apporach supporting HW/SW partitioning decisions for reconfigurable System-on-Chip: Master's thesis

Keyphrases

• Master's Thesis 100%
• Estimation Approaches 100%
• Reconfigurable System-on-chip 100%
• HW-SW Partitioning 100%
• General Purpose Processor 75%
• SimpleScalar 50%
• Field Programmable Gate Arrays 25%
• Resource Utilization 25%
• Processor Core 25%
• Supporting Facilities 25%
• Mappability 25%
• High-level Synthesis 25%
• Mapping Application 25%
• Area Constraint 25%
• Speedup Ratio 25%
• Hardware Accelerator 25%
• Reconfigurable Logic Unit 25%

Computer Science

• General Purpose Processor 100%
• Reconfigurable System 100%
• System-on-Chip 100%
• Speed-up 33%
• Hardware Accelerator 33%
• Reconfigurable Logic 33%
• Resource Utilisation 33%
• Processor Core 33%
• High Level Synthesis 33%
• Field Programmable Gate Arrays 33%

INIS

• synthesis 100%
• errors 66%
• levels 33%
• information 33%
• resources 33%
• applications 33%
• speed 33%
• mapping 33%
• constraints 33%
• units 33%
• accuracy 33%
• accelerators 33%