Evaluation of platform architecture performance using abstract instruction-level workload models

Jari Kreku, Tarja Kauppi, Juha-Pekka Soininen

    Research output: Chapter in Book/Report/Conference proceedingConference article in proceedingsScientificpeer-review

    10 Citations (Scopus)


    Evaluation of platform performance is critical in the optimisation and validation of integrated application domain specific multiprocessor systems. This paper describes a method for creating abstract instruction-level workload models from source code, and a method for modelling multiprocessor platforms. The approaches are validated by simulating complex use cases in a multiprocessor platform and comparing some of the results to measurements obtained from a prototype product. The approach is targeted at defining architecture parameters and to feature feasibility studies at product concept creation phase.
    Original languageEnglish
    Title of host publication2004 International Symposium on System-on-Chip Proceedings
    PublisherIEEE Institute of Electrical and Electronic Engineers
    ISBN (Print)978-0-7803-8558-0
    Publication statusPublished - 2004
    MoE publication typeA4 Article in a conference publication
    Event2004 International Symposium on System-on-Chip - Tampere, Finland
    Duration: 16 Nov 200418 Nov 2004


    Conference2004 International Symposium on System-on-Chip


    • Multiprocessor system
    • performance simulation
    • SystemC


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