Evaluation of platform architecture performance using abstract instruction-level workload models

Jari Kreku, Tarja Kauppi, Juha-Pekka Soininen

    Research output: Chapter in Book/Report/Conference proceedingConference article in proceedingsScientificpeer-review

    10 Citations (Scopus)

    Abstract

    Evaluation of platform performance is critical in the optimisation and validation of integrated application domain specific multiprocessor systems. This paper describes a method for creating abstract instruction-level workload models from source code, and a method for modelling multiprocessor platforms. The approaches are validated by simulating complex use cases in a multiprocessor platform and comparing some of the results to measurements obtained from a prototype product. The approach is targeted at defining architecture parameters and to feature feasibility studies at product concept creation phase.
    Original languageEnglish
    Title of host publication2004 International Symposium on System-on-Chip Proceedings
    PublisherIEEE Institute of Electrical and Electronic Engineers
    Pages43-48
    ISBN (Print)0-7803-8558-6
    DOIs
    Publication statusPublished - 2004
    MoE publication typeA4 Article in a conference publication
    Event2004 International Symposium on System-on-Chip - Tampere, Finland
    Duration: 16 Nov 200418 Nov 2004

    Conference

    Conference2004 International Symposium on System-on-Chip
    CountryFinland
    CityTampere
    Period16/11/0418/11/04

    Keywords

    • Multiprocessor system
    • performance simulation
    • SystemC

    Cite this

    Kreku, J., Kauppi, T., & Soininen, J-P. (2004). Evaluation of platform architecture performance using abstract instruction-level workload models. In 2004 International Symposium on System-on-Chip Proceedings (pp. 43-48). IEEE Institute of Electrical and Electronic Engineers. https://doi.org/10.1109/ISSOC.2004.1411143