Evaluation of platform architecture performance using abstract instruction-level workload models

Jari Kreku; Tarja Kauppi; Juha-Pekka Soininen

doi:10.1109/ISSOC.2004.1411143

Evaluation of platform architecture performance using abstract instruction-level workload models

Jari Kreku, Tarja Kauppi, Juha-Pekka Soininen

Research output: Chapter in Book/Report/Conference proceeding › Conference article in proceedings › Scientific › peer-review

10 Citations (Scopus)

Abstract

Evaluation of platform performance is critical in the optimisation and validation of integrated application domain specific multiprocessor systems. This paper describes a method for creating abstract instruction-level workload models from source code, and a method for modelling multiprocessor platforms. The approaches are validated by simulating complex use cases in a multiprocessor platform and comparing some of the results to measurements obtained from a prototype product. The approach is targeted at defining architecture parameters and to feature feasibility studies at product concept creation phase.

Original language	English
Title of host publication	2004 International Symposium on System-on-Chip Proceedings
Publisher	IEEE Institute of Electrical and Electronic Engineers
Pages	43-48
ISBN (Print)	978-0-7803-8558-0
DOIs	https://doi.org/10.1109/ISSOC.2004.1411143
Publication status	Published - 2004
MoE publication type	A4 Article in a conference publication
Event	2004 International Symposium on System-on-Chip - Tampere, Finland Duration: 16 Nov 2004 → 18 Nov 2004

Conference

Conference	2004 International Symposium on System-on-Chip
Country/Territory	Finland
City	Tampere
Period	16/11/04 → 18/11/04

Keywords

Multiprocessor system
performance simulation
SystemC

Access to Document

10.1109/ISSOC.2004.1411143

Cite this

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title = "Evaluation of platform architecture performance using abstract instruction-level workload models",

abstract = "Evaluation of platform performance is critical in the optimisation and validation of integrated application domain specific multiprocessor systems. This paper describes a method for creating abstract instruction-level workload models from source code, and a method for modelling multiprocessor platforms. The approaches are validated by simulating complex use cases in a multiprocessor platform and comparing some of the results to measurements obtained from a prototype product. The approach is targeted at defining architecture parameters and to feature feasibility studies at product concept creation phase.",

keywords = "Multiprocessor system, performance simulation, SystemC",

author = "Jari Kreku and Tarja Kauppi and Juha-Pekka Soininen",

note = "Project code: E4SU00110; 2004 International Symposium on System-on-Chip ; Conference date: 16-11-2004 Through 18-11-2004",

year = "2004",

doi = "10.1109/ISSOC.2004.1411143",

language = "English",

isbn = "978-0-7803-8558-0",

pages = "43--48",

booktitle = "2004 International Symposium on System-on-Chip Proceedings",

publisher = "IEEE Institute of Electrical and Electronic Engineers",

address = "United States",

}

Kreku, J, Kauppi, T & Soininen, J-P 2004, Evaluation of platform architecture performance using abstract instruction-level workload models. in 2004 International Symposium on System-on-Chip Proceedings. IEEE Institute of Electrical and Electronic Engineers, pp. 43-48, 2004 International Symposium on System-on-Chip, Tampere, Finland, 16/11/04. https://doi.org/10.1109/ISSOC.2004.1411143

Evaluation of platform architecture performance using abstract instruction-level workload models. / Kreku, Jari; Kauppi, Tarja; Soininen, Juha-Pekka.
2004 International Symposium on System-on-Chip Proceedings. IEEE Institute of Electrical and Electronic Engineers, 2004. p. 43-48.

Research output: Chapter in Book/Report/Conference proceeding › Conference article in proceedings › Scientific › peer-review

TY - GEN

T1 - Evaluation of platform architecture performance using abstract instruction-level workload models

AU - Kreku, Jari

AU - Kauppi, Tarja

AU - Soininen, Juha-Pekka

N1 - Project code: E4SU00110

PY - 2004

Y1 - 2004

N2 - Evaluation of platform performance is critical in the optimisation and validation of integrated application domain specific multiprocessor systems. This paper describes a method for creating abstract instruction-level workload models from source code, and a method for modelling multiprocessor platforms. The approaches are validated by simulating complex use cases in a multiprocessor platform and comparing some of the results to measurements obtained from a prototype product. The approach is targeted at defining architecture parameters and to feature feasibility studies at product concept creation phase.

AB - Evaluation of platform performance is critical in the optimisation and validation of integrated application domain specific multiprocessor systems. This paper describes a method for creating abstract instruction-level workload models from source code, and a method for modelling multiprocessor platforms. The approaches are validated by simulating complex use cases in a multiprocessor platform and comparing some of the results to measurements obtained from a prototype product. The approach is targeted at defining architecture parameters and to feature feasibility studies at product concept creation phase.

KW - Multiprocessor system

KW - performance simulation

KW - SystemC

U2 - 10.1109/ISSOC.2004.1411143

DO - 10.1109/ISSOC.2004.1411143

M3 - Conference article in proceedings

SN - 978-0-7803-8558-0

SP - 43

EP - 48

BT - 2004 International Symposium on System-on-Chip Proceedings

PB - IEEE Institute of Electrical and Electronic Engineers

T2 - 2004 International Symposium on System-on-Chip

Y2 - 16 November 2004 through 18 November 2004

ER -

Evaluation of platform architecture performance using abstract instruction-level workload models

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Keywords

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