Exploration of a heterogeneous concentrated-sparse on-chip interconnect for energy efficien multicore architecture

Thomas Canhao Xy, Ville Leppänen, Martti Forsell

Research output: Chapter in Book/Report/Conference proceedingConference article in proceedingsScientificpeer-review

3 Citations (Scopus)

Abstract

We present a novel heterogeneous on-chip inter- connect, concentrated-sparse mesh, suitable for high efficiency multicore architectures. The topology is implemented by taking the advantages of both concentrated mesh and sparse mesh networks. The object of the proposed heterogeneous network is to improve performance of the system when running real applica- tions with self-similar, hot-spot and bursty traffic. While regular mesh network has been used widely in on-chip interconnect, con- centrated mesh improves average network latency by reducing the number of intermediate network resources. However with high traffic requirements, the limited network bandwidth leads to congestion and performance bottleneck. On the other hand, sparse mesh improves network bandwidth by increasing the number of routers and links, therefore the network can process more hot-spot and bursty traffic than regular and concentrated mesh networks. The weakness of sparse mesh is that, with low traffic injection, the network latency of packets can be higher than other networks. Furthermore the size of the interconnect can become unrealistic for large systems. The proposed heterogeneous interconnect utilizes two networks for processing different traffic. We explore and discuss traffic injection behaviour of several applications. The heterogeneous network is analyzed in details. We investigate a routing algorithm and a mapping algorithm designed for the proposed network. Comparative results are provided by using a full system simulation environment. Results demonstrate that the proposed interconnect improves the average network latency and energy delay product by 15.7% and 44.7%, respectively, compared with regular mesh network.
Original languageEnglish
Title of host publicationProceedings
Subtitle of host publicationIEEE International Conference on Computer and Information Technology, CIT 2014
PublisherInstitute of Electrical and Electronic Engineers IEEE
Pages204-211
ISBN (Electronic)978-1-4799-6239-6
DOIs
Publication statusPublished - 2014
MoE publication typeA4 Article in a conference publication
Event14th IEEE International Conference on Computer and Information Technology, CIT 2014 - Xi'an, Shaanxi, China
Duration: 11 Sep 201413 Sep 2014

Conference

Conference14th IEEE International Conference on Computer and Information Technology, CIT 2014
Abbreviated titleCIT 2014
CountryChina
CityXi'an, Shaanxi
Period11/09/1413/09/14

Fingerprint

Heterogeneous networks
Bandwidth
Routing algorithms
Routers
Telecommunication traffic
Telecommunication links
Topology
Processing

Cite this

Xy, T. C., Leppänen, V., & Forsell, M. (2014). Exploration of a heterogeneous concentrated-sparse on-chip interconnect for energy efficien multicore architecture. In Proceedings: IEEE International Conference on Computer and Information Technology, CIT 2014 (pp. 204-211). Institute of Electrical and Electronic Engineers IEEE. https://doi.org/10.1109/CIT.2014.16
Xy, Thomas Canhao ; Leppänen, Ville ; Forsell, Martti. / Exploration of a heterogeneous concentrated-sparse on-chip interconnect for energy efficien multicore architecture. Proceedings: IEEE International Conference on Computer and Information Technology, CIT 2014. Institute of Electrical and Electronic Engineers IEEE, 2014. pp. 204-211
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title = "Exploration of a heterogeneous concentrated-sparse on-chip interconnect for energy efficien multicore architecture",
abstract = "We present a novel heterogeneous on-chip inter- connect, concentrated-sparse mesh, suitable for high efficiency multicore architectures. The topology is implemented by taking the advantages of both concentrated mesh and sparse mesh networks. The object of the proposed heterogeneous network is to improve performance of the system when running real applica- tions with self-similar, hot-spot and bursty traffic. While regular mesh network has been used widely in on-chip interconnect, con- centrated mesh improves average network latency by reducing the number of intermediate network resources. However with high traffic requirements, the limited network bandwidth leads to congestion and performance bottleneck. On the other hand, sparse mesh improves network bandwidth by increasing the number of routers and links, therefore the network can process more hot-spot and bursty traffic than regular and concentrated mesh networks. The weakness of sparse mesh is that, with low traffic injection, the network latency of packets can be higher than other networks. Furthermore the size of the interconnect can become unrealistic for large systems. The proposed heterogeneous interconnect utilizes two networks for processing different traffic. We explore and discuss traffic injection behaviour of several applications. The heterogeneous network is analyzed in details. We investigate a routing algorithm and a mapping algorithm designed for the proposed network. Comparative results are provided by using a full system simulation environment. Results demonstrate that the proposed interconnect improves the average network latency and energy delay product by 15.7{\%} and 44.7{\%}, respectively, compared with regular mesh network.",
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Xy, TC, Leppänen, V & Forsell, M 2014, Exploration of a heterogeneous concentrated-sparse on-chip interconnect for energy efficien multicore architecture. in Proceedings: IEEE International Conference on Computer and Information Technology, CIT 2014. Institute of Electrical and Electronic Engineers IEEE, pp. 204-211, 14th IEEE International Conference on Computer and Information Technology, CIT 2014, Xi'an, Shaanxi, China, 11/09/14. https://doi.org/10.1109/CIT.2014.16

Exploration of a heterogeneous concentrated-sparse on-chip interconnect for energy efficien multicore architecture. / Xy, Thomas Canhao; Leppänen, Ville; Forsell, Martti.

Proceedings: IEEE International Conference on Computer and Information Technology, CIT 2014. Institute of Electrical and Electronic Engineers IEEE, 2014. p. 204-211.

Research output: Chapter in Book/Report/Conference proceedingConference article in proceedingsScientificpeer-review

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AB - We present a novel heterogeneous on-chip inter- connect, concentrated-sparse mesh, suitable for high efficiency multicore architectures. The topology is implemented by taking the advantages of both concentrated mesh and sparse mesh networks. The object of the proposed heterogeneous network is to improve performance of the system when running real applica- tions with self-similar, hot-spot and bursty traffic. While regular mesh network has been used widely in on-chip interconnect, con- centrated mesh improves average network latency by reducing the number of intermediate network resources. However with high traffic requirements, the limited network bandwidth leads to congestion and performance bottleneck. On the other hand, sparse mesh improves network bandwidth by increasing the number of routers and links, therefore the network can process more hot-spot and bursty traffic than regular and concentrated mesh networks. The weakness of sparse mesh is that, with low traffic injection, the network latency of packets can be higher than other networks. Furthermore the size of the interconnect can become unrealistic for large systems. The proposed heterogeneous interconnect utilizes two networks for processing different traffic. We explore and discuss traffic injection behaviour of several applications. The heterogeneous network is analyzed in details. We investigate a routing algorithm and a mapping algorithm designed for the proposed network. Comparative results are provided by using a full system simulation environment. Results demonstrate that the proposed interconnect improves the average network latency and energy delay product by 15.7% and 44.7%, respectively, compared with regular mesh network.

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Xy TC, Leppänen V, Forsell M. Exploration of a heterogeneous concentrated-sparse on-chip interconnect for energy efficien multicore architecture. In Proceedings: IEEE International Conference on Computer and Information Technology, CIT 2014. Institute of Electrical and Electronic Engineers IEEE. 2014. p. 204-211 https://doi.org/10.1109/CIT.2014.16