Extending platform-based design to network on chip systems

Juha-Pekka Soininen; Axel Jantsch; Martti Forsell; Antti Pelkonen; Jari Kreku; Shashi Kumar

doi:10.1109/ICVD.2003.1183169

Extending platform-based design to network on chip systems

Juha-Pekka Soininen, Axel Jantsch, Martti Forsell, Antti Pelkonen, Jari Kreku, Shashi Kumar

Research output: Chapter in Book/Report/Conference proceeding › Conference article in proceedings › Scientific › peer-review

14 Citations (Scopus)

Abstract

Exploitation of silicon capacity will require improvements in design productivity and more scalable system paradigms. Asynchronous message passing networks on chip (NOC) have been proposed as backbones for billion-transistor ASICs. We present a novel layered backbone-platform-system (BPS) design methodology for development of network-on-chip based products. It combines and extends the distributed, parallel, embedded and platform-based design concepts in order to manage the diversity and complexity of NOC-based systems. The reuse of communication principles in various platforms, the reuse of platforms in product differentiation, and system-level decision-support methods are the cornerstones of our methodology. The presented mappability estimation and workload simulations demonstrate the feasibility of such methods.

Original language	English
Title of host publication	Proceedings 16th International Conference on VLSI Design
Publisher	IEEE Institute of Electrical and Electronic Engineers
Pages	401-408
ISBN (Print)	0-7695-1868-0
DOIs	https://doi.org/10.1109/ICVD.2003.1183169
Publication status	Published - 2003
MoE publication type	A4 Article in a conference publication
Event	16th International Conference on VLSI Design - New Delhi, India Duration: 4 Jan 2003 → 8 Jan 2003

Publication series

Series	Proceedings of the IEEE International Conference on VLSI Design
Volume	16
ISSN	1063-9667

Conference

Conference	16th International Conference on VLSI Design
Country/Territory	India
City	New Delhi
Period	4/01/03 → 8/01/03

Access to Document

10.1109/ICVD.2003.1183169

Cite this

@inproceedings{dc5d560c515b4cb1bf097bbe0a474ce4,

title = "Extending platform-based design to network on chip systems",

abstract = "Exploitation of silicon capacity will require improvements in design productivity and more scalable system paradigms. Asynchronous message passing networks on chip (NOC) have been proposed as backbones for billion-transistor ASICs. We present a novel layered backbone-platform-system (BPS) design methodology for development of network-on-chip based products. It combines and extends the distributed, parallel, embedded and platform-based design concepts in order to manage the diversity and complexity of NOC-based systems. The reuse of communication principles in various platforms, the reuse of platforms in product differentiation, and system-level decision-support methods are the cornerstones of our methodology. The presented mappability estimation and workload simulations demonstrate the feasibility of such methods.",

author = "Juha-Pekka Soininen and Axel Jantsch and Martti Forsell and Antti Pelkonen and Jari Kreku and Shashi Kumar",

note = "Project code: E1SU00066; 16th International Conference on VLSI Design ; Conference date: 04-01-2003 Through 08-01-2003",

year = "2003",

doi = "10.1109/ICVD.2003.1183169",

language = "English",

isbn = "0-7695-1868-0",

series = "Proceedings of the IEEE International Conference on VLSI Design",

publisher = "IEEE Institute of Electrical and Electronic Engineers",

pages = "401--408",

booktitle = "Proceedings 16th International Conference on VLSI Design",

address = "United States",

}

Soininen, J-P, Jantsch, A, Forsell, M, Pelkonen, A, Kreku, J & Kumar, S 2003, Extending platform-based design to network on chip systems. in Proceedings 16th International Conference on VLSI Design. IEEE Institute of Electrical and Electronic Engineers, Proceedings of the IEEE International Conference on VLSI Design, vol. 16, pp. 401-408, 16th International Conference on VLSI Design, New Delhi, India, 4/01/03. https://doi.org/10.1109/ICVD.2003.1183169

Extending platform-based design to network on chip systems. / Soininen, Juha-Pekka; Jantsch, Axel; Forsell, Martti et al.
Proceedings 16th International Conference on VLSI Design. IEEE Institute of Electrical and Electronic Engineers, 2003. p. 401-408 (Proceedings of the IEEE International Conference on VLSI Design, Vol. 16).

Research output: Chapter in Book/Report/Conference proceeding › Conference article in proceedings › Scientific › peer-review

TY - GEN

T1 - Extending platform-based design to network on chip systems

AU - Soininen, Juha-Pekka

AU - Jantsch, Axel

AU - Forsell, Martti

AU - Pelkonen, Antti

AU - Kreku, Jari

AU - Kumar, Shashi

N1 - Project code: E1SU00066

PY - 2003

Y1 - 2003

N2 - Exploitation of silicon capacity will require improvements in design productivity and more scalable system paradigms. Asynchronous message passing networks on chip (NOC) have been proposed as backbones for billion-transistor ASICs. We present a novel layered backbone-platform-system (BPS) design methodology for development of network-on-chip based products. It combines and extends the distributed, parallel, embedded and platform-based design concepts in order to manage the diversity and complexity of NOC-based systems. The reuse of communication principles in various platforms, the reuse of platforms in product differentiation, and system-level decision-support methods are the cornerstones of our methodology. The presented mappability estimation and workload simulations demonstrate the feasibility of such methods.

AB - Exploitation of silicon capacity will require improvements in design productivity and more scalable system paradigms. Asynchronous message passing networks on chip (NOC) have been proposed as backbones for billion-transistor ASICs. We present a novel layered backbone-platform-system (BPS) design methodology for development of network-on-chip based products. It combines and extends the distributed, parallel, embedded and platform-based design concepts in order to manage the diversity and complexity of NOC-based systems. The reuse of communication principles in various platforms, the reuse of platforms in product differentiation, and system-level decision-support methods are the cornerstones of our methodology. The presented mappability estimation and workload simulations demonstrate the feasibility of such methods.

U2 - 10.1109/ICVD.2003.1183169

DO - 10.1109/ICVD.2003.1183169

M3 - Conference article in proceedings

SN - 0-7695-1868-0

T3 - Proceedings of the IEEE International Conference on VLSI Design

SP - 401

EP - 408

BT - Proceedings 16th International Conference on VLSI Design

PB - IEEE Institute of Electrical and Electronic Engineers

T2 - 16th International Conference on VLSI Design

Y2 - 4 January 2003 through 8 January 2003

ER -

Extending platform-based design to network on chip systems

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