Extending platform-based design to network on chip systems

Juha-Pekka Soininen, Axel Jantsch, Martti Forsell, Antti Pelkonen, Jari Kreku, Shashi Kumar

    Research output: Chapter in Book/Report/Conference proceedingConference article in proceedingsScientificpeer-review

    14 Citations (Scopus)


    Exploitation of silicon capacity will require improvements in design productivity and more scalable system paradigms. Asynchronous message passing networks on chip (NOC) have been proposed as backbones for billion-transistor ASICs. We present a novel layered backbone-platform-system (BPS) design methodology for development of network-on-chip based products. It combines and extends the distributed, parallel, embedded and platform-based design concepts in order to manage the diversity and complexity of NOC-based systems. The reuse of communication principles in various platforms, the reuse of platforms in product differentiation, and system-level decision-support methods are the cornerstones of our methodology. The presented mappability estimation and workload simulations demonstrate the feasibility of such methods.
    Original languageEnglish
    Title of host publicationProceedings 16th International Conference on VLSI Design
    PublisherIEEE Institute of Electrical and Electronic Engineers
    ISBN (Print)0-7695-1868-0
    Publication statusPublished - 2003
    MoE publication typeA4 Article in a conference publication
    Event16th International Conference on VLSI Design - New Delhi, India
    Duration: 4 Jan 20038 Jan 2003

    Publication series

    SeriesProceedings of the IEEE International Conference on VLSI Design


    Conference16th International Conference on VLSI Design
    CityNew Delhi


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