Fabrication of edgeless detectors on 6" high resistive SOI wafers

The presentation gives an insight into the state-of-the-art 3D processing on 6" (150 mm) high resistive silicon-on-insulator (SOI) wafers. Utilization of bonded support wafer in the final detector or during the fabrication of the detector, allows fabrication of very thin microstrip detectors, and trench etching through the wafer during the process of the 3D and edgeless detectors. Presentation summarizes the first fabrication run with SEM images, reveals the issues and lessons learned in the 3D processing on 6" wafer. A straight forward and fast process to fabricate edgeless detec-tors is proposed and the first results of the prototypes are presented. The process relies on the sidewall ion-implantation and it excludes multiple ICP-etching steps; slow and wafer damaging polysilicon fill-ing; and all planarization steps.