Fabrication of silicon based through-wafer interconnects for advanced chip scale packaging

Fan Ji (Corresponding Author), Seppo Leppävuori, Ismo Luusua, Kimmo Henttinen, Simo Eränen, Iiro Hietanen, Mikko Juntunen

Research output: Contribution to journalArticleScientificpeer-review

14 Citations (Scopus)

Abstract

This paper presents a fabrication method to achieve through-wafer interconnects (TWIs) by etching, filling and grinding in sequence. Based on this method, advanced chip scale packaging (CSP) is performed. Compared to flip-chip technology, silicon based sensors or actuators, especially large scale detector arrays, can be assembled into a system with the sensing surface upwards, and electrical signals can then be extracted from the back side of the chip without sacrificing the front sensing surface by using TWIs. In addition, it also makes 3-D chip stacking possible. Generally speaking, less than 1.5 pF capacitance and 240 Ω resistance are measured from the fabricated wafer. In order to better integrate the TWIs into different sensor systems, the ability to vary the capacitance of the TWIs is discussed based on a metal-oxide-semiconductor (MOS) model. From leakage current simulation results, possible defects during the processing of TWIs are addressed and detected by introducing different failure mechanisms of the insulation of the TWIs. As a result, the fabrication of TWIs and their related CSP procedure have proved that it is a promising technology for a range of sensor applications.
Original languageEnglish
Pages (from-to)405-412
JournalSensors and Actuators A: Physical
Volume142
Issue number1
DOIs
Publication statusPublished - 2008
MoE publication typeA1 Journal article-refereed

Fingerprint

Silicon
packaging
Packaging
chips
wafers
Fabrication
fabrication
Sensors
silicon
Capacitance
Semiconductor device models
Leakage currents
Insulation
Etching
Actuators
Metals
Detectors
sensors
Defects
capacitance

Keywords

  • Through-wafer interconnects (TWIs)
  • Chip scale packaging (CSP)
  • Metal-oxide-semiconductor (MOS)
  • Failure mechanism

Cite this

Ji, F., Leppävuori, S., Luusua, I., Henttinen, K., Eränen, S., Hietanen, I., & Juntunen, M. (2008). Fabrication of silicon based through-wafer interconnects for advanced chip scale packaging. Sensors and Actuators A: Physical, 142(1), 405-412. https://doi.org/10.1016/j.sna.2007.02.030
Ji, Fan ; Leppävuori, Seppo ; Luusua, Ismo ; Henttinen, Kimmo ; Eränen, Simo ; Hietanen, Iiro ; Juntunen, Mikko. / Fabrication of silicon based through-wafer interconnects for advanced chip scale packaging. In: Sensors and Actuators A: Physical. 2008 ; Vol. 142, No. 1. pp. 405-412.
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abstract = "This paper presents a fabrication method to achieve through-wafer interconnects (TWIs) by etching, filling and grinding in sequence. Based on this method, advanced chip scale packaging (CSP) is performed. Compared to flip-chip technology, silicon based sensors or actuators, especially large scale detector arrays, can be assembled into a system with the sensing surface upwards, and electrical signals can then be extracted from the back side of the chip without sacrificing the front sensing surface by using TWIs. In addition, it also makes 3-D chip stacking possible. Generally speaking, less than 1.5 pF capacitance and 240 Ω resistance are measured from the fabricated wafer. In order to better integrate the TWIs into different sensor systems, the ability to vary the capacitance of the TWIs is discussed based on a metal-oxide-semiconductor (MOS) model. From leakage current simulation results, possible defects during the processing of TWIs are addressed and detected by introducing different failure mechanisms of the insulation of the TWIs. As a result, the fabrication of TWIs and their related CSP procedure have proved that it is a promising technology for a range of sensor applications.",
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Ji, F, Leppävuori, S, Luusua, I, Henttinen, K, Eränen, S, Hietanen, I & Juntunen, M 2008, 'Fabrication of silicon based through-wafer interconnects for advanced chip scale packaging', Sensors and Actuators A: Physical, vol. 142, no. 1, pp. 405-412. https://doi.org/10.1016/j.sna.2007.02.030

Fabrication of silicon based through-wafer interconnects for advanced chip scale packaging. / Ji, Fan (Corresponding Author); Leppävuori, Seppo; Luusua, Ismo; Henttinen, Kimmo; Eränen, Simo; Hietanen, Iiro; Juntunen, Mikko.

In: Sensors and Actuators A: Physical, Vol. 142, No. 1, 2008, p. 405-412.

Research output: Contribution to journalArticleScientificpeer-review

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AU - Ji, Fan

AU - Leppävuori, Seppo

AU - Luusua, Ismo

AU - Henttinen, Kimmo

AU - Eränen, Simo

AU - Hietanen, Iiro

AU - Juntunen, Mikko

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N2 - This paper presents a fabrication method to achieve through-wafer interconnects (TWIs) by etching, filling and grinding in sequence. Based on this method, advanced chip scale packaging (CSP) is performed. Compared to flip-chip technology, silicon based sensors or actuators, especially large scale detector arrays, can be assembled into a system with the sensing surface upwards, and electrical signals can then be extracted from the back side of the chip without sacrificing the front sensing surface by using TWIs. In addition, it also makes 3-D chip stacking possible. Generally speaking, less than 1.5 pF capacitance and 240 Ω resistance are measured from the fabricated wafer. In order to better integrate the TWIs into different sensor systems, the ability to vary the capacitance of the TWIs is discussed based on a metal-oxide-semiconductor (MOS) model. From leakage current simulation results, possible defects during the processing of TWIs are addressed and detected by introducing different failure mechanisms of the insulation of the TWIs. As a result, the fabrication of TWIs and their related CSP procedure have proved that it is a promising technology for a range of sensor applications.

AB - This paper presents a fabrication method to achieve through-wafer interconnects (TWIs) by etching, filling and grinding in sequence. Based on this method, advanced chip scale packaging (CSP) is performed. Compared to flip-chip technology, silicon based sensors or actuators, especially large scale detector arrays, can be assembled into a system with the sensing surface upwards, and electrical signals can then be extracted from the back side of the chip without sacrificing the front sensing surface by using TWIs. In addition, it also makes 3-D chip stacking possible. Generally speaking, less than 1.5 pF capacitance and 240 Ω resistance are measured from the fabricated wafer. In order to better integrate the TWIs into different sensor systems, the ability to vary the capacitance of the TWIs is discussed based on a metal-oxide-semiconductor (MOS) model. From leakage current simulation results, possible defects during the processing of TWIs are addressed and detected by introducing different failure mechanisms of the insulation of the TWIs. As a result, the fabrication of TWIs and their related CSP procedure have proved that it is a promising technology for a range of sensor applications.

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