Fabrication of SOI micromechanical devices: Dissertation

Research output: ThesisDissertation

Abstract

This work reports on studies and the fabrication process development of micromechanical silicon-on-insulator (SOI) devices. SOI is a promising starting material for fabrication of single crystal silicon micromechanical devices and basis for monolithic integration of sensors and integrated circuits. The buried oxide layer of an SOI wafer offers an excellent etch stop layer for silicon etching and sacrificial layer for fabrication of capacitive sensors. Deep silicon etching is studied and the aspect ratio dependency of the etch rate and loading effects are described and modeled. The etch rate of the deep silicon etching process is modeled with a simple flow conductance model, which takes into account only the initial etch rate and reaction probability and flow resistance of the etched feature. The used model predicts qualitatively the aspect-ratio-dependent etch rate for varying trench widths and rectangular shapes. The design related loading can be modeled and the effects of the loading can be minimized with proper etch mask design. The basic SOI micromechanics process is described and the drawbacks and limitations of the process are discussed. Improvements to the process are introduced as well as IR microscopy as a new method to inspect the sacrificial etch length of the SOI structure. A new fabrication process for SOI micromechanics has been developed that alleviates metallization problems during the wet etching of the sacrificial layer. The process is based on forming closed cavities under the structure layer of SOI with the help of a semi-permeable polysilicon film. Prototype SOI device fabrication results are presented. High Q single crystal silicon micro resonators have potential for replacing bulky quartz resonators in clock circuits. Monolithic integration of micromechanical devices and an integrated circuit has been demonstrated with the developed process using the embedded vacuum cavities.
Original languageEnglish
QualificationDoctor Degree
Awarding Institution
  • Aalto University
Award date15 Apr 2005
Place of PublicationEspoo
Publisher
Print ISBNs951-38-6435-9
Electronic ISBNs951-38-6436-7
Publication statusPublished - 2005
MoE publication typeG5 Doctoral dissertation (article)

Fingerprint

Fabrication
Silicon
Etching
Micromechanics
Integrated circuits
Aspect ratio
Resonators
Single crystals
Capacitive sensors
Wet etching
Metallizing
Polysilicon
Masks
Quartz
Clocks
Microscopic examination
Vacuum
Oxides
Networks (circuits)
Sensors

Keywords

  • silicon-on-insulator
  • SOI
  • micromechanics
  • MEMS
  • microfabrication
  • HARMST
  • DRIE
  • etching
  • vacuum cavities
  • resonators
  • monolithic integration

Cite this

Kiihamäki, J. (2005). Fabrication of SOI micromechanical devices: Dissertation. Espoo: VTT Technical Research Centre of Finland.
Kiihamäki, Jyrki. / Fabrication of SOI micromechanical devices : Dissertation. Espoo : VTT Technical Research Centre of Finland, 2005. 121 p.
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abstract = "This work reports on studies and the fabrication process development of micromechanical silicon-on-insulator (SOI) devices. SOI is a promising starting material for fabrication of single crystal silicon micromechanical devices and basis for monolithic integration of sensors and integrated circuits. The buried oxide layer of an SOI wafer offers an excellent etch stop layer for silicon etching and sacrificial layer for fabrication of capacitive sensors. Deep silicon etching is studied and the aspect ratio dependency of the etch rate and loading effects are described and modeled. The etch rate of the deep silicon etching process is modeled with a simple flow conductance model, which takes into account only the initial etch rate and reaction probability and flow resistance of the etched feature. The used model predicts qualitatively the aspect-ratio-dependent etch rate for varying trench widths and rectangular shapes. The design related loading can be modeled and the effects of the loading can be minimized with proper etch mask design. The basic SOI micromechanics process is described and the drawbacks and limitations of the process are discussed. Improvements to the process are introduced as well as IR microscopy as a new method to inspect the sacrificial etch length of the SOI structure. A new fabrication process for SOI micromechanics has been developed that alleviates metallization problems during the wet etching of the sacrificial layer. The process is based on forming closed cavities under the structure layer of SOI with the help of a semi-permeable polysilicon film. Prototype SOI device fabrication results are presented. High Q single crystal silicon micro resonators have potential for replacing bulky quartz resonators in clock circuits. Monolithic integration of micromechanical devices and an integrated circuit has been demonstrated with the developed process using the embedded vacuum cavities.",
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author = "Jyrki Kiiham{\"a}ki",
year = "2005",
language = "English",
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publisher = "VTT Technical Research Centre of Finland",
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}

Kiihamäki, J 2005, 'Fabrication of SOI micromechanical devices: Dissertation', Doctor Degree, Aalto University, Espoo.

Fabrication of SOI micromechanical devices : Dissertation. / Kiihamäki, Jyrki.

Espoo : VTT Technical Research Centre of Finland, 2005. 121 p.

Research output: ThesisDissertation

TY - THES

T1 - Fabrication of SOI micromechanical devices

T2 - Dissertation

AU - Kiihamäki, Jyrki

PY - 2005

Y1 - 2005

N2 - This work reports on studies and the fabrication process development of micromechanical silicon-on-insulator (SOI) devices. SOI is a promising starting material for fabrication of single crystal silicon micromechanical devices and basis for monolithic integration of sensors and integrated circuits. The buried oxide layer of an SOI wafer offers an excellent etch stop layer for silicon etching and sacrificial layer for fabrication of capacitive sensors. Deep silicon etching is studied and the aspect ratio dependency of the etch rate and loading effects are described and modeled. The etch rate of the deep silicon etching process is modeled with a simple flow conductance model, which takes into account only the initial etch rate and reaction probability and flow resistance of the etched feature. The used model predicts qualitatively the aspect-ratio-dependent etch rate for varying trench widths and rectangular shapes. The design related loading can be modeled and the effects of the loading can be minimized with proper etch mask design. The basic SOI micromechanics process is described and the drawbacks and limitations of the process are discussed. Improvements to the process are introduced as well as IR microscopy as a new method to inspect the sacrificial etch length of the SOI structure. A new fabrication process for SOI micromechanics has been developed that alleviates metallization problems during the wet etching of the sacrificial layer. The process is based on forming closed cavities under the structure layer of SOI with the help of a semi-permeable polysilicon film. Prototype SOI device fabrication results are presented. High Q single crystal silicon micro resonators have potential for replacing bulky quartz resonators in clock circuits. Monolithic integration of micromechanical devices and an integrated circuit has been demonstrated with the developed process using the embedded vacuum cavities.

AB - This work reports on studies and the fabrication process development of micromechanical silicon-on-insulator (SOI) devices. SOI is a promising starting material for fabrication of single crystal silicon micromechanical devices and basis for monolithic integration of sensors and integrated circuits. The buried oxide layer of an SOI wafer offers an excellent etch stop layer for silicon etching and sacrificial layer for fabrication of capacitive sensors. Deep silicon etching is studied and the aspect ratio dependency of the etch rate and loading effects are described and modeled. The etch rate of the deep silicon etching process is modeled with a simple flow conductance model, which takes into account only the initial etch rate and reaction probability and flow resistance of the etched feature. The used model predicts qualitatively the aspect-ratio-dependent etch rate for varying trench widths and rectangular shapes. The design related loading can be modeled and the effects of the loading can be minimized with proper etch mask design. The basic SOI micromechanics process is described and the drawbacks and limitations of the process are discussed. Improvements to the process are introduced as well as IR microscopy as a new method to inspect the sacrificial etch length of the SOI structure. A new fabrication process for SOI micromechanics has been developed that alleviates metallization problems during the wet etching of the sacrificial layer. The process is based on forming closed cavities under the structure layer of SOI with the help of a semi-permeable polysilicon film. Prototype SOI device fabrication results are presented. High Q single crystal silicon micro resonators have potential for replacing bulky quartz resonators in clock circuits. Monolithic integration of micromechanical devices and an integrated circuit has been demonstrated with the developed process using the embedded vacuum cavities.

KW - silicon-on-insulator

KW - SOI

KW - micromechanics

KW - MEMS

KW - microfabrication

KW - HARMST

KW - DRIE

KW - etching

KW - vacuum cavities

KW - resonators

KW - monolithic integration

M3 - Dissertation

SN - 951-38-6435-9

T3 - VTT Publications

PB - VTT Technical Research Centre of Finland

CY - Espoo

ER -

Kiihamäki J. Fabrication of SOI micromechanical devices: Dissertation. Espoo: VTT Technical Research Centre of Finland, 2005. 121 p.