Fast processor core selection for WLAN modem using mappability estimation

Juha-Pekka Soininen, Jari Kreku, Yang Qu, Martti Forsell

Research output: Chapter in Book/Report/Conference proceedingConference article in proceedingsScientificpeer-review

Abstract

A new class of System-on-Chips (SOC) called Network-on-Chips (NOC) has recently been proposed to solve the architectural and design complexity issues of future SOCs. The design and selection of an architecture for a NOC is, however, not a trivial task, because it requires expertise in parallel computing ranging from detailed processor microarchitectures to complex system architectures and from instruction-level parallelism (ILP) to thread-level parallelism (TLP) at various ganularities. We have developed a simulation environment called IPSMSim for evaluating parallel architectures based on a network of homogeneous computing resources and exploring the effect of architectural solutions on ILP and TLP exploitation on those architectures. IPSMSim supports currently parametric single and multithreaded processors, various interconnection topologies and memory module organizations realizing the shared memory and message passing programming models. IPSMSim has tools for compiling and loading native assembler programs, importing RISC programs as well as translating and optimizing them to native architecture, and collecting various types of execution and communication statistics. IPSMSim has been successfully applied to a number of researches ranging from microarchitecture-level to system-level evaluations
Original languageEnglish
Title of host publicationProceedings of the 2002 20th IEEE NORCHIP Conference
Subtitle of host publicationthe Nordic Event in ASIC Design
Place of PublicationCopenhagen
PublisherTechnoconsult
Pages171-176
ISBN (Print)87-982637-4-9
Publication statusPublished - 2002
MoE publication typeA4 Article in a conference publication
Event20th NORCHIP conference 2002 - Copenhagen, Denmark
Duration: 11 Nov 200212 Nov 2002

Conference

Conference20th NORCHIP conference 2002
CountryDenmark
CityCopenhagen
Period11/11/0212/11/02

Keywords

  • codesign
  • mappability
  • design Space Exploration
  • system-on-Chip

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    Soininen, J-P., Kreku, J., Qu, Y., & Forsell, M. (2002). Fast processor core selection for WLAN modem using mappability estimation. In Proceedings of the 2002 20th IEEE NORCHIP Conference: the Nordic Event in ASIC Design (pp. 171-176). Technoconsult.