Fault-tolerant architecture for nanoelectronic digital logic

    Research output: Chapter in Book/Report/Conference proceedingConference article in proceedingsScientificpeer-review

    2 Citations (Scopus)

    Abstract

    This paper presents a new system architecture for implementing fault-tolerant information processing.
    The proposed structure relies on simple processing elements (PEs) arranged into a regular locally-interconnected array. Such an approach is a favorable way of implementing circuits with inherently unreliable nanodevices.
    Different network operations are achieved through binary programmable interconnections. The array can be divided into a set of software-defined segments for implementing functions with different levels of complexity and redundancy, assuring the system versatility and flexibility.
    The examples of basic Boolean operations are presented. The error correction mechanism is explained and its impact on fault-tolerance is briefly analyzed.
    Original languageEnglish
    Title of host publicationProceedings
    Subtitle of host publicationInternational Conference on Signals and Electronic Systems, ICSES 2008
    PublisherIEEE Institute of Electrical and Electronic Engineers
    Pages545-548
    ISBN (Print)978-83-88309-47-2, 978-83-88309-52-6
    DOIs
    Publication statusPublished - 2008
    MoE publication typeA4 Article in a conference publication
    EventInternational Conference on Signals and Electronic Systems, ICSES 2008 - Krakow, Poland
    Duration: 14 Sep 200817 Sep 2008

    Conference

    ConferenceInternational Conference on Signals and Electronic Systems, ICSES 2008
    Abbreviated titleICSES 2008
    CountryPoland
    CityKrakow
    Period14/09/0817/09/08

    Fingerprint

    Nanoelectronics
    Error correction
    Fault tolerance
    Redundancy
    Networks (circuits)
    Processing

    Keywords

    • cellular architecture
    • fault tolerance
    • gate arrays
    • nanotechnology

    Cite this

    Flak, J. (2008). Fault-tolerant architecture for nanoelectronic digital logic. In Proceedings: International Conference on Signals and Electronic Systems, ICSES 2008 (pp. 545-548). IEEE Institute of Electrical and Electronic Engineers . https://doi.org/10.1109/ICSES.2008.4673493
    Flak, Jacek. / Fault-tolerant architecture for nanoelectronic digital logic. Proceedings: International Conference on Signals and Electronic Systems, ICSES 2008. IEEE Institute of Electrical and Electronic Engineers , 2008. pp. 545-548
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    Flak, J 2008, Fault-tolerant architecture for nanoelectronic digital logic. in Proceedings: International Conference on Signals and Electronic Systems, ICSES 2008. IEEE Institute of Electrical and Electronic Engineers , pp. 545-548, International Conference on Signals and Electronic Systems, ICSES 2008, Krakow, Poland, 14/09/08. https://doi.org/10.1109/ICSES.2008.4673493

    Fault-tolerant architecture for nanoelectronic digital logic. / Flak, Jacek.

    Proceedings: International Conference on Signals and Electronic Systems, ICSES 2008. IEEE Institute of Electrical and Electronic Engineers , 2008. p. 545-548.

    Research output: Chapter in Book/Report/Conference proceedingConference article in proceedingsScientificpeer-review

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    Flak J. Fault-tolerant architecture for nanoelectronic digital logic. In Proceedings: International Conference on Signals and Electronic Systems, ICSES 2008. IEEE Institute of Electrical and Electronic Engineers . 2008. p. 545-548 https://doi.org/10.1109/ICSES.2008.4673493