Fault-tolerant architecture for nanoelectronic digital logic

    Research output: Chapter in Book/Report/Conference proceedingConference article in proceedingsScientificpeer-review

    2 Citations (Scopus)


    This paper presents a new system architecture for implementing fault-tolerant information processing.
    The proposed structure relies on simple processing elements (PEs) arranged into a regular locally-interconnected array. Such an approach is a favorable way of implementing circuits with inherently unreliable nanodevices.
    Different network operations are achieved through binary programmable interconnections. The array can be divided into a set of software-defined segments for implementing functions with different levels of complexity and redundancy, assuring the system versatility and flexibility.
    The examples of basic Boolean operations are presented. The error correction mechanism is explained and its impact on fault-tolerance is briefly analyzed.
    Original languageEnglish
    Title of host publicationProceedings
    Subtitle of host publicationInternational Conference on Signals and Electronic Systems, ICSES 2008
    PublisherIEEE Institute of Electrical and Electronic Engineers
    ISBN (Print)978-83-88309-47-2, 978-83-88309-52-6
    Publication statusPublished - 2008
    MoE publication typeA4 Article in a conference publication
    EventInternational Conference on Signals and Electronic Systems, ICSES 2008 - Krakow, Poland
    Duration: 14 Sept 200817 Sept 2008


    ConferenceInternational Conference on Signals and Electronic Systems, ICSES 2008
    Abbreviated titleICSES 2008


    • cellular architecture
    • fault tolerance
    • gate arrays
    • nanotechnology


    Dive into the research topics of 'Fault-tolerant architecture for nanoelectronic digital logic'. Together they form a unique fingerprint.

    Cite this