Fault-tolerant architecture for nanoelectronic digital logic

Jacek Flak

doi:10.1109/ICSES.2008.4673493

Fault-tolerant architecture for nanoelectronic digital logic

Research output: Chapter in Book/Report/Conference proceeding › Conference article in proceedings › Scientific › peer-review

2 Citations (Scopus)

Abstract

This paper presents a new system architecture for implementing fault-tolerant information processing.
The proposed structure relies on simple processing elements (PEs) arranged into a regular locally-interconnected array. Such an approach is a favorable way of implementing circuits with inherently unreliable nanodevices.
Different network operations are achieved through binary programmable interconnections. The array can be divided into a set of software-defined segments for implementing functions with different levels of complexity and redundancy, assuring the system versatility and flexibility.
The examples of basic Boolean operations are presented. The error correction mechanism is explained and its impact on fault-tolerance is briefly analyzed.

Original language	English
Title of host publication	Proceedings
Subtitle of host publication	International Conference on Signals and Electronic Systems, ICSES 2008
Publisher	IEEE Institute of Electrical and Electronic Engineers
Pages	545-548
ISBN (Print)	978-83-88309-47-2, 978-83-88309-52-6
DOIs	https://doi.org/10.1109/ICSES.2008.4673493
Publication status	Published - 2008
MoE publication type	A4 Article in a conference publication
Event	International Conference on Signals and Electronic Systems, ICSES 2008 - Krakow, Poland Duration: 14 Sept 2008 → 17 Sept 2008

Conference

Conference	International Conference on Signals and Electronic Systems, ICSES 2008
Abbreviated title	ICSES 2008
Country/Territory	Poland
City	Krakow
Period	14/09/08 → 17/09/08

Keywords

cellular architecture
fault tolerance
gate arrays
nanotechnology

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10.1109/ICSES.2008.4673493

Cite this

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title = "Fault-tolerant architecture for nanoelectronic digital logic",

abstract = "This paper presents a new system architecture for implementing fault-tolerant information processing. The proposed structure relies on simple processing elements (PEs) arranged into a regular locally-interconnected array. Such an approach is a favorable way of implementing circuits with inherently unreliable nanodevices. Different network operations are achieved through binary programmable interconnections. The array can be divided into a set of software-defined segments for implementing functions with different levels of complexity and redundancy, assuring the system versatility and flexibility. The examples of basic Boolean operations are presented. The error correction mechanism is explained and its impact on fault-tolerance is briefly analyzed.",

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note = "International Conference on Signals and Electronic Systems, ICSES 2008, ICSES 2008 ; Conference date: 14-09-2008 Through 17-09-2008",

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Flak, J 2008, Fault-tolerant architecture for nanoelectronic digital logic. in Proceedings: International Conference on Signals and Electronic Systems, ICSES 2008. IEEE Institute of Electrical and Electronic Engineers, pp. 545-548, International Conference on Signals and Electronic Systems, ICSES 2008, Krakow, Poland, 14/09/08. https://doi.org/10.1109/ICSES.2008.4673493

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N2 - This paper presents a new system architecture for implementing fault-tolerant information processing. The proposed structure relies on simple processing elements (PEs) arranged into a regular locally-interconnected array. Such an approach is a favorable way of implementing circuits with inherently unreliable nanodevices. Different network operations are achieved through binary programmable interconnections. The array can be divided into a set of software-defined segments for implementing functions with different levels of complexity and redundancy, assuring the system versatility and flexibility. The examples of basic Boolean operations are presented. The error correction mechanism is explained and its impact on fault-tolerance is briefly analyzed.

AB - This paper presents a new system architecture for implementing fault-tolerant information processing. The proposed structure relies on simple processing elements (PEs) arranged into a regular locally-interconnected array. Such an approach is a favorable way of implementing circuits with inherently unreliable nanodevices. Different network operations are achieved through binary programmable interconnections. The array can be divided into a set of software-defined segments for implementing functions with different levels of complexity and redundancy, assuring the system versatility and flexibility. The examples of basic Boolean operations are presented. The error correction mechanism is explained and its impact on fault-tolerance is briefly analyzed.

KW - cellular architecture

KW - fault tolerance

KW - gate arrays

KW - nanotechnology

U2 - 10.1109/ICSES.2008.4673493

DO - 10.1109/ICSES.2008.4673493

M3 - Conference article in proceedings

SN - 978-83-88309-47-2

SN - 978-83-88309-52-6

SP - 545

EP - 548

BT - Proceedings

PB - IEEE Institute of Electrical and Electronic Engineers

T2 - International Conference on Signals and Electronic Systems, ICSES 2008

Y2 - 14 September 2008 through 17 September 2008

ER -

Fault-tolerant architecture for nanoelectronic digital logic

Abstract

Conference

Keywords

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