Fault-tolerant programmable logic array for nanoelectronics

Jacek Flak (Corresponding Author), M. Laiho

    Research output: Contribution to journalArticleScientificpeer-review

    5 Citations (Scopus)

    Abstract

    This paper presents the architecture for a nanoelectronic logic system in which a regular array of logic gates with programmable interconnections is accompanied by a data transmitter and receiver as well as program registers and a controller. Binary programmable interconnections assure system versatility by providing the means of computing different logic operations. They also allow setting the redundancy level via the number of columns clustered to compute a certain function. A system operation is explained and visualized with a number of examples. The embedded scheme of fault tolerance can effectively mitigate permanent, as well as transient, faults. Some implementation and performance aspects are approached through simulations of single‐electron tunneling structures. However, the proposed architectural concept is generic and can be applied to systems implemented with alternative nanotechnologies.
    Original languageEnglish
    Pages (from-to)1233-1247
    Number of pages15
    JournalInternational Journal of Circuit Theory and Applications
    Volume40
    Issue number12
    DOIs
    Publication statusPublished - 2012
    MoE publication typeA1 Journal article-refereed

    Keywords

    • Fault tolerance
    • hybrid circuits
    • nanoelectronics
    • programmable logic array
    • single-electron devices

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