FDSOI versus BULK CMOS at 28 nm node which technology for ultra-low power design?

Jani Mäkipää, Olivier Billoint

Research output: Chapter in Book/Report/Conference proceedingConference article in proceedingsScientificpeer-review

9 Citations (Scopus)

Abstract

Compared to BULK CMOS, FDSOI (Fully-Depleted Silicon-On-Insulator) introduces an ultra-thin buried oxide (BOX) layer and a dopant-free channel, which provides better performance and enhances ultra-low power (ULP) operation. To investigate benefits of utilizing FDSOI for ULP design, FDSOI and BULK CMOS 28 nm nodes are compared by simulating a test circuit. Threshold voltage tuning by back-plane biasing (BPB) for FDSOI and bulk biasing (BB) for BULK is analyzed. Contours of constant energy with minimum energy points (MEPs) are shown as well as energy delay products (EDPs). Simulation results show that FDSOI forward BPB can be used effectively to control operating frequency, EDP and MEP operation. Implications of the results are discussed last to give an overview how FDSOI performance gain over BULK CMOS can support in ULP design.
Original languageEnglish
Title of host publication2013 IEEE International Symposium on Circuits and Systems (ISCAS2013)
PublisherInstitute of Electrical and Electronic Engineers IEEE
Pages554-557
ISBN (Electronic)978-1-4673-5762-3, 978-1-4673-5761-6
ISBN (Print)978-1-4673-5760-9
DOIs
Publication statusPublished - 2013
MoE publication typeA4 Article in a conference publication
EventIEEE International Symposium on Circuits and Systems, ISCAS 2013 - Beijing, China
Duration: 19 May 201323 May 2013

Conference

ConferenceIEEE International Symposium on Circuits and Systems, ISCAS 2013
Abbreviated titleISCAS2013
CountryChina
CityBeijing
Period19/05/1323/05/13

Fingerprint

Silicon
Threshold voltage
Tuning
Doping (additives)
Oxides
Networks (circuits)

Keywords

  • back plane biasing
  • BULK
  • bulk biasing
  • FDSOI
  • minimum energy operation
  • sub-threshold operation

Cite this

Mäkipää, J., & Billoint, O. (2013). FDSOI versus BULK CMOS at 28 nm node which technology for ultra-low power design? In 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013) (pp. 554-557). Institute of Electrical and Electronic Engineers IEEE. https://doi.org/10.1109/ISCAS.2013.6571903
Mäkipää, Jani ; Billoint, Olivier. / FDSOI versus BULK CMOS at 28 nm node which technology for ultra-low power design?. 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013). Institute of Electrical and Electronic Engineers IEEE, 2013. pp. 554-557
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Mäkipää, J & Billoint, O 2013, FDSOI versus BULK CMOS at 28 nm node which technology for ultra-low power design? in 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013). Institute of Electrical and Electronic Engineers IEEE, pp. 554-557, IEEE International Symposium on Circuits and Systems, ISCAS 2013, Beijing, China, 19/05/13. https://doi.org/10.1109/ISCAS.2013.6571903

FDSOI versus BULK CMOS at 28 nm node which technology for ultra-low power design? / Mäkipää, Jani; Billoint, Olivier.

2013 IEEE International Symposium on Circuits and Systems (ISCAS2013). Institute of Electrical and Electronic Engineers IEEE, 2013. p. 554-557.

Research output: Chapter in Book/Report/Conference proceedingConference article in proceedingsScientificpeer-review

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Mäkipää J, Billoint O. FDSOI versus BULK CMOS at 28 nm node which technology for ultra-low power design? In 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013). Institute of Electrical and Electronic Engineers IEEE. 2013. p. 554-557 https://doi.org/10.1109/ISCAS.2013.6571903