FDSOI versus BULK CMOS at 28 nm node which technology for ultra-low power design?

Jani Mäkipää; Olivier Billoint

doi:10.1109/ISCAS.2013.6571903

FDSOI versus BULK CMOS at 28 nm node which technology for ultra-low power design?

Jani Mäkipää
, Olivier Billoint

VTT Technical Research Centre of Finland

Commissariat a l'Energie Atomique et aux Energies Alternatives (CEA)

Research output: Chapter in Book/Report/Conference proceeding › Conference article in proceedings › Scientific › peer-review

16 Citations (Scopus)

Abstract

Compared to BULK CMOS, FDSOI (Fully-Depleted Silicon-On-Insulator) introduces an ultra-thin buried oxide (BOX) layer and a dopant-free channel, which provides better performance and enhances ultra-low power (ULP) operation. To investigate benefits of utilizing FDSOI for ULP design, FDSOI and BULK CMOS 28 nm nodes are compared by simulating a test circuit. Threshold voltage tuning by back-plane biasing (BPB) for FDSOI and bulk biasing (BB) for BULK is analyzed. Contours of constant energy with minimum energy points (MEPs) are shown as well as energy delay products (EDPs). Simulation results show that FDSOI forward BPB can be used effectively to control operating frequency, EDP and MEP operation. Implications of the results are discussed last to give an overview how FDSOI performance gain over BULK CMOS can support in ULP design.

Original language	English
Title of host publication	2013 IEEE International Symposium on Circuits and Systems (ISCAS2013)
Publisher	IEEE Institute of Electrical and Electronic Engineers
Pages	554-557
ISBN (Electronic)	978-1-4673-5762-3, 978-1-4673-5761-6
ISBN (Print)	978-1-4673-5760-9
DOIs	https://doi.org/10.1109/ISCAS.2013.6571903
Publication status	Published - 2013
MoE publication type	A4 Article in a conference publication
Event	IEEE International Symposium on Circuits and Systems, ISCAS 2013 - Beijing, China Duration: 19 May 2013 → 23 May 2013

Conference

Conference	IEEE International Symposium on Circuits and Systems, ISCAS 2013
Abbreviated title	ISCAS2013
Country/Territory	China
City	Beijing
Period	19/05/13 → 23/05/13

Keywords

back plane biasing
BULK
bulk biasing
FDSOI
minimum energy operation
sub-threshold operation

Access to Document

10.1109/ISCAS.2013.6571903

Cite this

@inproceedings{402c6b42f7b540e3ba6942abdcfde139,

title = "FDSOI versus BULK CMOS at 28 nm node which technology for ultra-low power design?",

abstract = "Compared to BULK CMOS, FDSOI (Fully-Depleted Silicon-On-Insulator) introduces an ultra-thin buried oxide (BOX) layer and a dopant-free channel, which provides better performance and enhances ultra-low power (ULP) operation. To investigate benefits of utilizing FDSOI for ULP design, FDSOI and BULK CMOS 28 nm nodes are compared by simulating a test circuit. Threshold voltage tuning by back-plane biasing (BPB) for FDSOI and bulk biasing (BB) for BULK is analyzed. Contours of constant energy with minimum energy points (MEPs) are shown as well as energy delay products (EDPs). Simulation results show that FDSOI forward BPB can be used effectively to control operating frequency, EDP and MEP operation. Implications of the results are discussed last to give an overview how FDSOI performance gain over BULK CMOS can support in ULP design.",

keywords = "back plane biasing, BULK, bulk biasing, FDSOI, minimum energy operation, sub-threshold operation",

author = "Jani M{\"a}kip{\"a}{\"a} and Olivier Billoint",

year = "2013",

doi = "10.1109/ISCAS.2013.6571903",

language = "English",

isbn = "978-1-4673-5760-9",

pages = "554--557",

booktitle = "2013 IEEE International Symposium on Circuits and Systems (ISCAS2013)",

publisher = "IEEE Institute of Electrical and Electronic Engineers",

address = "United States",

note = "IEEE International Symposium on Circuits and Systems, ISCAS 2013, ISCAS2013 ; Conference date: 19-05-2013 Through 23-05-2013",

}

Mäkipää, J & Billoint, O 2013, FDSOI versus BULK CMOS at 28 nm node which technology for ultra-low power design? in 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013). IEEE Institute of Electrical and Electronic Engineers, pp. 554-557, IEEE International Symposium on Circuits and Systems, ISCAS 2013, Beijing, China, 19/05/13. https://doi.org/10.1109/ISCAS.2013.6571903

FDSOI versus BULK CMOS at 28 nm node which technology for ultra-low power design? / Mäkipää, Jani; Billoint, Olivier.
2013 IEEE International Symposium on Circuits and Systems (ISCAS2013). IEEE Institute of Electrical and Electronic Engineers, 2013. p. 554-557.

Research output: Chapter in Book/Report/Conference proceeding › Conference article in proceedings › Scientific › peer-review