Flexible DSP platform for various workload patterns

    Research output: Chapter in Book/Report/Conference proceedingConference article in proceedingsScientificpeer-review

    Abstract

    A flexible DSP platform that utilises pre-designed IP cores, such as DSP and RISC processors, advanced coprocessors for critical functions and configurable memory organisation is presented. ADSL, Hiper-LAN2 subset and MPEG2 decoding algorithms have been analysed as a basis of IHIP architecture design.
    Original languageEnglish
    Title of host publicationProceedings of the 2001 Finnish Signal Processing Symposium FINSIG'01
    PublisherHelsinki University of Technology
    Pages43-46
    ISBN (Electronic)951-22-5496-4
    ISBN (Print)951-22-5497-2
    Publication statusPublished - 2001
    MoE publication typeA4 Article in a conference publication
    EventFinnish Signal Processing Symposium, FINSIG'01 - Espoo, Finland
    Duration: 5 Jun 20015 Jun 2001

    Publication series

    SeriesHelsinki University of Technology: Laboratory of Signal Processing and Computer Technology. Report
    Number33
    ISSN1456-6907

    Conference

    ConferenceFinnish Signal Processing Symposium, FINSIG'01
    Country/TerritoryFinland
    CityEspoo
    Period5/06/015/06/01

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