TY - GEN
T1 - Flexible DSP platform for various workload patterns
AU - Pelkonen, Antti
AU - Roivainen, Jussi
AU - Soininen, Juha-Pekka
PY - 2001
Y1 - 2001
N2 - A flexible DSP platform that utilises pre-designed IP cores, such as DSP and RISC processors, advanced coprocessors for critical functions and configurable memory organisation is presented. ADSL, Hiper-LAN2 subset and MPEG2 decoding algorithms have been analysed as a basis of IHIP architecture design.
AB - A flexible DSP platform that utilises pre-designed IP cores, such as DSP and RISC processors, advanced coprocessors for critical functions and configurable memory organisation is presented. ADSL, Hiper-LAN2 subset and MPEG2 decoding algorithms have been analysed as a basis of IHIP architecture design.
M3 - Conference article in proceedings
SN - 951-22-5497-2
T3 - Helsinki University of Technology: Laboratory of Signal Processing and Computer Technology. Report
SP - 43
EP - 46
BT - Proceedings of the 2001 Finnish Signal Processing Symposium FINSIG'01
PB - Helsinki University of Technology
T2 - Finnish Signal Processing Symposium, FINSIG'01
Y2 - 5 June 2001 through 5 June 2001
ER -