Floating-point supportive pipeline for emulated shared memory architectures

Matti Forsell (Inventor)

Research output: PatentPatent


A processor architecture arrangement for emulated shared memory (ESM) architectures, comprising a number of multi-threaded processors each provided with interleaved inter-thread pipeline (400) and a plurality of functional units (402, 402b, 402c, 404, 404b, 404c) for carrying out arithmetic and logical operations on data, wherein the pipeline (400) comprises at least two operatively parallel pipeline branches (414, 416), first pipeline branch (414) comprising a first sub-group of said plurality of functional units (402, 402b, 402c), such as ALUs (arithmetic logic unit), arranged for carrying out integer operations, and second pipeline branch (416) comprising a second, non-overlapping sub-group of said plurality of functional units (404, 404b, 404c), such as FPUs (floating point unit), arranged for carrying out floating point operations, and further wherein one or more of the functional units (404b) of at least said second sub-group arranged for floating point operations are located operatively in parallel with the memory access segment (412, 412a) of the pipeline (400).

Patent family as of 19.10.2021
CN105814538 A 20160727 CN201480066972 20141023      
CN105814538 B 20200414 CN201480066972 20141023      
DE602013058717 D1 20190829 DE201360058717T 20131023      
EP2866138 A1 20150429 EP20130189861 20131023      
EP2866138 B1 20190807 EP20130189861 20131023      
JP2016534433 T2 20161104 JP20160526075T 20141023      
JP6469674 B2 20190213 JP20160526075T 20141023      
KR102279200 B1 20210719 KR20167013403 20141023      
KR20160074638 A 20160628 KR20167013403 20141023      
US2016283249 AA 20160929 US20140031285 20141023      
WO15059362 A1 20150430 WO2014FI50804 20141023

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Original languageEnglish
Patent numberEP2866138
IPCG06F 9/ 38 A I
Priority date23/10/13
Publication statusPublished - 29 Apr 2015
MoE publication typeH1 Granted patent


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