FPGA implementation of a channel estimator for a distributed multiple antenna OFDM system: Master's Thesis

Mikko Hiivala

    Research output: ThesisMaster's thesis

    Abstract

    Multiple antenna techniques applied to orthogonal frequency division multiplexing (OFDM) will be featured in future fourth generation wireless transmission systems (4G). The high spectral efficiency of OFDM combined with improved resilience against multipath propagation and fading achieved through multiple antenna diversity techniques make the high transfer rate mobile communications promised by 4G possible. In distributed antenna systems, the antennas centrally attached to base stations are distributed across the cells to enable shorter transmission distances and use of lower transmit power, which reduces interference and enables higher transmission capacity. The use of multiple antennas requires accurate channel state knowledge at the receiver for the demodulation of the received symbols to be possible, necessitating estimation of the channel state. In channel estimators based on transmitting known pilot symbols, an orthogonal pilot set is needed per every transmitting antenna. As the number of transmitting antennas can grow large in distributed antenna systems, transmitting pilots multiplexed with the data symbols can cause considerable overhead and reduce data throughput significantly. By superimposing pilot symbols on data symbols at a fraction of the total transmit power, the effect of channel estimation overhead on data throughput can be avoided. The goal in this work was to study the feasibility of using and implementing channel estimation based on superimposed pilots in a distributed multiple antenna OFDM system. For this purpose, different channel estimation algorithms were studied and their performances were compared by software simulations. Algorithms selected based on the study were converted into a very-high-speed integrated circuit hardware description language (VHDL) model, targeted to be synthesized onto a field programmable gate array (FPGA) based prototyping platform for real-time simulations. The software simulations indicate that the performance of the superimposed channel estimator is strongly dependant on how effectively the underlying data symbols are removed from the estimates of the pilots, and on the other hand the ratio of transmit power allocated for pilots and data. Based on the algorithm study and software simulations, least squares estimation was chosen as the pilot estimation method, and piece-wise linear interpolation in the frequency domain as the channel estimate interpolation method. Averaging the pilot estimates over one OFDM frame in time direction was chosen as the method of removing the data symbols from the pilot estimates. According to the simulation results, the highest modulation order that could be supported by the system is six bits per symbol, resulting in a maximum uncoded channel bit rate of 565 Mbps. The hardware implementation achieved a maximum clock frequency of 112.3 MHz.
    Original languageEnglish
    QualificationMaster Degree
    Awarding Institution
    • University of Oulu
    Place of PublicationOulu
    Publisher
    Publication statusPublished - 2010
    MoE publication typeG2 Master's thesis, polytechnic Master's thesis

    Keywords

    • MIMO-OFDM
    • channel estimation
    • superimposed pilots
    • FPGA

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