FPGA implementation of the channelizer module in a WCDMA receiver

Master's thesis

Zhang Yan

Research output: ThesisMaster's thesisTheses

Abstract

In this master’s thesis, a digital channelizer for WCDMA base station receiver was designed and implemented using Xilinx Virtex-II FPGA. The channelization technique is a key element in the digital intermediate frequency (IF) wideband receiver architecture. It is used to isolate the independent communication channels contained within the wideband signal. This case study was part of the Heppu project in the ASIC design group of Nokia Networks, Sweden. The implementation needs to fulfil the functional requirements for the quick prototype from the Heppu project. The final results are tested by test vectors and compared with the results from ASIC implementation for the same module.
Original languageEnglish
QualificationMaster Degree
Awarding Institution
  • KTH Royal Institute of Technology
Place of PublicationStockholm
Publication statusPublished - 2004
MoE publication typeG2 Master's thesis, polytechnic Master's thesis

Fingerprint

Application specific integrated circuits
Field programmable gate arrays (FPGA)
Base stations

Keywords

  • ASIC
  • channelizer
  • communication channel
  • FPGA
  • intermediate frequency
  • receiver architecture
  • VHDL
  • WCDMA base station

Cite this

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title = "FPGA implementation of the channelizer module in a WCDMA receiver: Master's thesis",
abstract = "In this master’s thesis, a digital channelizer for WCDMA base station receiver was designed and implemented using Xilinx Virtex-II FPGA. The channelization technique is a key element in the digital intermediate frequency (IF) wideband receiver architecture. It is used to isolate the independent communication channels contained within the wideband signal. This case study was part of the Heppu project in the ASIC design group of Nokia Networks, Sweden. The implementation needs to fulfil the functional requirements for the quick prototype from the Heppu project. The final results are tested by test vectors and compared with the results from ASIC implementation for the same module.",
keywords = "ASIC, channelizer, communication channel, FPGA, intermediate frequency, receiver architecture, VHDL, WCDMA base station",
author = "Zhang Yan",
note = "CA: ELE KTH Microelectronics and Information Technology Master of Science Thesis IMIT/LECS-2004-20",
year = "2004",
language = "English",
school = "KTH Royal Institute of Technology",

}

Yan, Z 2004, 'FPGA implementation of the channelizer module in a WCDMA receiver: Master's thesis', Master Degree, KTH Royal Institute of Technology, Stockholm.

FPGA implementation of the channelizer module in a WCDMA receiver : Master's thesis. / Yan, Zhang.

Stockholm, 2004. 74 p.

Research output: ThesisMaster's thesisTheses

TY - THES

T1 - FPGA implementation of the channelizer module in a WCDMA receiver

T2 - Master's thesis

AU - Yan, Zhang

N1 - CA: ELE KTH Microelectronics and Information Technology Master of Science Thesis IMIT/LECS-2004-20

PY - 2004

Y1 - 2004

N2 - In this master’s thesis, a digital channelizer for WCDMA base station receiver was designed and implemented using Xilinx Virtex-II FPGA. The channelization technique is a key element in the digital intermediate frequency (IF) wideband receiver architecture. It is used to isolate the independent communication channels contained within the wideband signal. This case study was part of the Heppu project in the ASIC design group of Nokia Networks, Sweden. The implementation needs to fulfil the functional requirements for the quick prototype from the Heppu project. The final results are tested by test vectors and compared with the results from ASIC implementation for the same module.

AB - In this master’s thesis, a digital channelizer for WCDMA base station receiver was designed and implemented using Xilinx Virtex-II FPGA. The channelization technique is a key element in the digital intermediate frequency (IF) wideband receiver architecture. It is used to isolate the independent communication channels contained within the wideband signal. This case study was part of the Heppu project in the ASIC design group of Nokia Networks, Sweden. The implementation needs to fulfil the functional requirements for the quick prototype from the Heppu project. The final results are tested by test vectors and compared with the results from ASIC implementation for the same module.

KW - ASIC

KW - channelizer

KW - communication channel

KW - FPGA

KW - intermediate frequency

KW - receiver architecture

KW - VHDL

KW - WCDMA base station

M3 - Master's thesis

CY - Stockholm

ER -