FPGA implementation of the channelizer module in a WCDMA receiver: Master's thesis

Zhang Yan

Research output: ThesisMaster's thesis

Abstract

In this master’s thesis, a digital channelizer for WCDMA base station receiver was designed and implemented using Xilinx Virtex-II FPGA. The channelization technique is a key element in the digital intermediate frequency (IF) wideband receiver architecture. It is used to isolate the independent communication channels contained within the wideband signal. This case study was part of the Heppu project in the ASIC design group of Nokia Networks, Sweden. The implementation needs to fulfil the functional requirements for the quick prototype from the Heppu project. The final results are tested by test vectors and compared with the results from ASIC implementation for the same module.
Original languageEnglish
QualificationMaster Degree
Awarding Institution
  • KTH Royal Institute of Technology
Place of PublicationStockholm
Publication statusPublished - 2004
MoE publication typeG2 Master's thesis, polytechnic Master's thesis

Keywords

  • ASIC
  • channelizer
  • communication channel
  • FPGA
  • intermediate frequency
  • receiver architecture
  • VHDL
  • WCDMA base station

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