Fractional Delay Filter Based on the B-Spline Transform

Juuso Olkkonen, H. Olkkonen

Research output: Contribution to journalArticleScientificpeer-review

16 Citations (Scopus)

Abstract

Fractional delay filters (FDFs) have a key role in communication systems. FDFs produce a delay that is a fraction of the sampling period. In this letter, we introduce a framework based on the B-spline interpolation and decimation procedure for design of the FDFs. The method generates precise fractional delays and is easy to implement in microprocessor and VLSI environments
Original languageEnglish
Pages (from-to)97-100
JournalIEEE Signal Processing Letters
Volume14
Issue number2
DOIs
Publication statusPublished - 2007
MoE publication typeA1 Journal article-refereed

Keywords

  • B-splines
  • VLSI
  • delay filters
  • interpolation
  • signal sampling
  • splines (mathematics)
  • B-spline transform
  • FDF design
  • VLSI environment
  • communication system
  • decimation procedure
  • fractional delay filter
  • microprocessor
  • sampling period
  • very large scale integration

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