Fractional Delay Filter Based on the B-Spline Transform

Juuso Olkkonen; H. Olkkonen

doi:10.1109/LSP.2006.882103

Fractional Delay Filter Based on the B-Spline Transform

Juuso Olkkonen, H. Olkkonen

University of Eastern Finland

Research output: Contribution to journal › Article › Scientific › peer-review

21 Citations (Scopus)

Abstract

Fractional delay filters (FDFs) have a key role in communication systems. FDFs produce a delay that is a fraction of the sampling period. In this letter, we introduce a framework based on the B-spline interpolation and decimation procedure for design of the FDFs. The method generates precise fractional delays and is easy to implement in microprocessor and VLSI environments

Original language	English
Pages (from-to)	97-100
Journal	IEEE Signal Processing Letters
Volume	14
Issue number	2
DOIs	https://doi.org/10.1109/LSP.2006.882103
Publication status	Published - 2007
MoE publication type	A1 Journal article-refereed

Keywords

B-splines
VLSI
delay filters
interpolation
signal sampling
splines (mathematics)
B-spline transform
FDF design
VLSI environment
communication system
decimation procedure
fractional delay filter
microprocessor
sampling period
very large scale integration

Access to Document

10.1109/LSP.2006.882103

Cite this

@article{81d549e6d2b24c11b2da07fde6c71216,

title = "Fractional Delay Filter Based on the B-Spline Transform",

abstract = "Fractional delay filters (FDFs) have a key role in communication systems. FDFs produce a delay that is a fraction of the sampling period. In this letter, we introduce a framework based on the B-spline interpolation and decimation procedure for design of the FDFs. The method generates precise fractional delays and is easy to implement in microprocessor and VLSI environments",

keywords = "B-splines, VLSI, delay filters, interpolation, signal sampling, splines (mathematics), B-spline transform, FDF design, VLSI environment, communication system, decimation procedure, fractional delay filter, microprocessor, sampling period, very large scale integration",

author = "Juuso Olkkonen and H. Olkkonen",

year = "2007",

doi = "10.1109/LSP.2006.882103",

language = "English",

volume = "14",

pages = "97--100",

journal = "IEEE Signal Processing Letters",

issn = "1070-9908",

publisher = "IEEE Institute of Electrical and Electronic Engineers",

number = "2",

}

TY - JOUR

T1 - Fractional Delay Filter Based on the B-Spline Transform

AU - Olkkonen, Juuso

AU - Olkkonen, H.

PY - 2007

Y1 - 2007

N2 - Fractional delay filters (FDFs) have a key role in communication systems. FDFs produce a delay that is a fraction of the sampling period. In this letter, we introduce a framework based on the B-spline interpolation and decimation procedure for design of the FDFs. The method generates precise fractional delays and is easy to implement in microprocessor and VLSI environments

AB - Fractional delay filters (FDFs) have a key role in communication systems. FDFs produce a delay that is a fraction of the sampling period. In this letter, we introduce a framework based on the B-spline interpolation and decimation procedure for design of the FDFs. The method generates precise fractional delays and is easy to implement in microprocessor and VLSI environments

KW - B-splines

KW - VLSI

KW - delay filters

KW - interpolation

KW - signal sampling

KW - splines (mathematics)

KW - B-spline transform

KW - FDF design

KW - VLSI environment

KW - communication system

KW - decimation procedure

KW - fractional delay filter

KW - microprocessor

KW - sampling period

KW - very large scale integration

U2 - 10.1109/LSP.2006.882103

DO - 10.1109/LSP.2006.882103

M3 - Article

SN - 1070-9908

VL - 14

SP - 97

EP - 100

JO - IEEE Signal Processing Letters

JF - IEEE Signal Processing Letters

IS - 2

ER -

Fractional Delay Filter Based on the B-Spline Transform

Abstract

Keywords

Access to Document

Fingerprint

Cite this