Fractional Delay Filter Based on the B-Spline Transform

Juuso Olkkonen, H. Olkkonen

Research output: Contribution to journalArticleScientificpeer-review

15 Citations (Scopus)

Abstract

Fractional delay filters (FDFs) have a key role in communication systems. FDFs produce a delay that is a fraction of the sampling period. In this letter, we introduce a framework based on the B-spline interpolation and decimation procedure for design of the FDFs. The method generates precise fractional delays and is easy to implement in microprocessor and VLSI environments
Original languageEnglish
Pages (from-to)97-100
JournalIEEE Signal Processing Letters
Volume14
Issue number2
DOIs
Publication statusPublished - 2007
MoE publication typeA1 Journal article-refereed

Fingerprint

B-spline
Splines
Microprocessor chips
Interpolation
Communication systems
Fractional
Mathematical transformations
Transform
Filter
Sampling
Decimation
Spline Interpolation
Microprocessor
Communication Systems

Keywords

  • B-splines
  • VLSI
  • delay filters
  • interpolation
  • signal sampling
  • splines (mathematics)
  • B-spline transform
  • FDF design
  • VLSI environment
  • communication system
  • decimation procedure
  • fractional delay filter
  • microprocessor
  • sampling period
  • very large scale integration

Cite this

Olkkonen, Juuso ; Olkkonen, H. / Fractional Delay Filter Based on the B-Spline Transform. In: IEEE Signal Processing Letters. 2007 ; Vol. 14, No. 2. pp. 97-100.
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Fractional Delay Filter Based on the B-Spline Transform. / Olkkonen, Juuso; Olkkonen, H.

In: IEEE Signal Processing Letters, Vol. 14, No. 2, 2007, p. 97-100.

Research output: Contribution to journalArticleScientificpeer-review

TY - JOUR

T1 - Fractional Delay Filter Based on the B-Spline Transform

AU - Olkkonen, Juuso

AU - Olkkonen, H.

PY - 2007

Y1 - 2007

N2 - Fractional delay filters (FDFs) have a key role in communication systems. FDFs produce a delay that is a fraction of the sampling period. In this letter, we introduce a framework based on the B-spline interpolation and decimation procedure for design of the FDFs. The method generates precise fractional delays and is easy to implement in microprocessor and VLSI environments

AB - Fractional delay filters (FDFs) have a key role in communication systems. FDFs produce a delay that is a fraction of the sampling period. In this letter, we introduce a framework based on the B-spline interpolation and decimation procedure for design of the FDFs. The method generates precise fractional delays and is easy to implement in microprocessor and VLSI environments

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KW - VLSI

KW - delay filters

KW - interpolation

KW - signal sampling

KW - splines (mathematics)

KW - B-spline transform

KW - FDF design

KW - VLSI environment

KW - communication system

KW - decimation procedure

KW - fractional delay filter

KW - microprocessor

KW - sampling period

KW - very large scale integration

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DO - 10.1109/LSP.2006.882103

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EP - 100

JO - IEEE Signal Processing Letters

JF - IEEE Signal Processing Letters

SN - 1070-9908

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ER -