Frame synchronized ring: A bus concept for high speed processing applications

This paper introduces a high throughput bus concept, named “Frame Synchronized Ring” (FSR-bus). The bus is based on a ring topology, which is an economical way to construct an efficient interconnection network for high speed multiprocessor applications. The paper describes the bus structure, its timing arrangements, frame structure, medium access control algorithm, and explains its operation.

The performance of the bus is estimated using the models developed for slotted rings. To evaluate its efficiency, simulated throughput and transfer delays were compared to those of the traditional multidrop bus and the Orwell ring. Simulation models for each of the three buses were developed and run in cases when the traffic in the ring was uniformly and geometrically distributed. The results show that, in both traffic cases, the FSR-bus performs distinctly better than the multidrop bus. Compared to the Orwell ring, the FSR-bus is slightly better when the traffic is uniformly distributed and performs clearly better when the traffic is geometrically distributed.