Frame synchronized ring and its implementation

This publication presents the Frame Synchronized Ring (FSR), a multi-access inter-connection network. The FSR concept is based on a ring topology and a simple yet efficient distributed medium access control mechanism, which uses destination release policy. Performance of the bus is analysed, and the results of the mathematical analysis have been confirmed by computer simulation and by measurements with the prototype system. The design and implementation issues of the FSR are introduced, including a description of the first prototype, its performance characteristics, and electrical bus design considerations such as line termination, crosstalk, and achievable clock rate versus bus length. The prototype of the FSR is constructed using field programmable gate array chips, which enable a flexible way to implement prototypes. The bus width of 32 bits and system clock rate of 20 Mhz allow bit rates of over 600 Mbps per link. The next version of the FSR, constructed using ASIC components, will at least double the figures. Finally, some application aspects and horizons for the FSR are given. A real-time switch for digitized video, based on the prototype, is presented as a concrete application example.