Harnessing Si CMOS technology for quantum information

L. Hutin; B. Bertrand; R. Maurand; M. Urdampilleta; B. Jadot; Heorhii Bohuslavskyi; L. Bourdet; Y.-M. Niquet; X. Jehl; S. Barraud; C. Bauerle; T. Meunier; M. Sanquer; S. De Franceschi; M. Vinet

doi:10.23919/snw.2017.8242337

Harnessing Si CMOS technology for quantum information

L. Hutin (Corresponding author), B. Bertrand, R. Maurand, M. Urdampilleta, B. Jadot, Heorhii Bohuslavskyi, L. Bourdet, Y.-M. Niquet, X. Jehl, S. Barraud, C. Bauerle, T. Meunier, M. Sanquer, S. De Franceschi, M. Vinet

Not published at VTT

Research output: Chapter in Book/Report/Conference proceeding › Conference article in proceedings › Scientific › peer-review

Abstract

We present some recent progress towards the implementation of the basic building blocks of quantum information processing derived from a Si CMOS technology platform. In our approach, characterized by an emphasis on foundry compatibility in terms of processes and materials, the so-called qubits are encoded in the spin degree of freedom of gate-confined elementary charges. After introducing various qubit manipulation, coupling and readout schemes, we discuss some prospects for scalability, and in particular some potential advantages of the FDSOI technology.

Original language	English
Title of host publication	2017 Silicon Nanoelectronics Workshop, SNW 2017
Publisher	IEEE Institute of Electrical and Electronic Engineers
Pages	141-142
ISBN (Electronic)	978-4-8634-8647-8
DOIs	https://doi.org/10.23919/snw.2017.8242337
Publication status	Published - Jun 2017
MoE publication type	A4 Article in a conference publication

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10.23919/snw.2017.8242337

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Hutin, L., Bertrand, B., Maurand, R., Urdampilleta, M., Jadot, B., Bohuslavskyi, H., Bourdet, L., Niquet, Y.-M., Jehl, X., Barraud, S., Bauerle, C., Meunier, T., Sanquer, M., Franceschi, S. D., & Vinet, M. (2017). Harnessing Si CMOS technology for quantum information. In 2017 Silicon Nanoelectronics Workshop, SNW 2017 (pp. 141-142). Article 8242337 IEEE Institute of Electrical and Electronic Engineers. https://doi.org/10.23919/snw.2017.8242337

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title = "Harnessing Si CMOS technology for quantum information",

abstract = "We present some recent progress towards the implementation of the basic building blocks of quantum information processing derived from a Si CMOS technology platform. In our approach, characterized by an emphasis on foundry compatibility in terms of processes and materials, the so-called qubits are encoded in the spin degree of freedom of gate-confined elementary charges. After introducing various qubit manipulation, coupling and readout schemes, we discuss some prospects for scalability, and in particular some potential advantages of the FDSOI technology.",

author = "L. Hutin and B. Bertrand and R. Maurand and M. Urdampilleta and B. Jadot and Heorhii Bohuslavskyi and L. Bourdet and Y.-M. Niquet and X. Jehl and S. Barraud and C. Bauerle and T. Meunier and M. Sanquer and Franceschi, {S. De} and M. Vinet",

note = "Publisher Copyright: {\textcopyright} 2017 JSAP.",

year = "2017",

month = jun,

doi = "10.23919/snw.2017.8242337",

language = "English",

pages = "141--142",

booktitle = "2017 Silicon Nanoelectronics Workshop, SNW 2017",

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Hutin, L, Bertrand, B, Maurand, R, Urdampilleta, M, Jadot, B, Bohuslavskyi, H, Bourdet, L, Niquet, Y-M, Jehl, X, Barraud, S, Bauerle, C, Meunier, T, Sanquer, M, Franceschi, SD & Vinet, M 2017, Harnessing Si CMOS technology for quantum information. in 2017 Silicon Nanoelectronics Workshop, SNW 2017., 8242337, IEEE Institute of Electrical and Electronic Engineers, pp. 141-142. https://doi.org/10.23919/snw.2017.8242337

Harnessing Si CMOS technology for quantum information. / Hutin, L. (Corresponding author); Bertrand, B.; Maurand, R. et al.
2017 Silicon Nanoelectronics Workshop, SNW 2017. IEEE Institute of Electrical and Electronic Engineers, 2017. p. 141-142 8242337.

Research output: Chapter in Book/Report/Conference proceeding › Conference article in proceedings › Scientific › peer-review

TY - GEN

T1 - Harnessing Si CMOS technology for quantum information

AU - Hutin, L.

AU - Bertrand, B.

AU - Maurand, R.

AU - Urdampilleta, M.

AU - Jadot, B.

AU - Bohuslavskyi, Heorhii

AU - Bourdet, L.

AU - Niquet, Y.-M.

AU - Jehl, X.

AU - Barraud, S.

AU - Bauerle, C.

AU - Meunier, T.

AU - Sanquer, M.

AU - Franceschi, S. De

AU - Vinet, M.

PY - 2017/6

Y1 - 2017/6

N2 - We present some recent progress towards the implementation of the basic building blocks of quantum information processing derived from a Si CMOS technology platform. In our approach, characterized by an emphasis on foundry compatibility in terms of processes and materials, the so-called qubits are encoded in the spin degree of freedom of gate-confined elementary charges. After introducing various qubit manipulation, coupling and readout schemes, we discuss some prospects for scalability, and in particular some potential advantages of the FDSOI technology.

AB - We present some recent progress towards the implementation of the basic building blocks of quantum information processing derived from a Si CMOS technology platform. In our approach, characterized by an emphasis on foundry compatibility in terms of processes and materials, the so-called qubits are encoded in the spin degree of freedom of gate-confined elementary charges. After introducing various qubit manipulation, coupling and readout schemes, we discuss some prospects for scalability, and in particular some potential advantages of the FDSOI technology.

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U2 - 10.23919/snw.2017.8242337

DO - 10.23919/snw.2017.8242337

M3 - Conference article in proceedings

SP - 141

EP - 142

BT - 2017 Silicon Nanoelectronics Workshop, SNW 2017

PB - IEEE Institute of Electrical and Electronic Engineers

ER -

Harnessing Si CMOS technology for quantum information

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