Abstract
| Original language | English |
|---|---|
| Title of host publication | Proceedings |
| Subtitle of host publication | IEEE 63rd Electronic Components and Technology Conference, ECTC 2013 |
| Publisher | Institute of Electrical and Electronic Engineers IEEE |
| Pages | 1500-1507 |
| ISBN (Electronic) | 978-1-4799-0232-3 |
| ISBN (Print) | 978-1-4799-0233-0 |
| DOIs | |
| Publication status | Published - 2013 |
| MoE publication type | Not Eligible |
| Event | IEEE 63rd Electronic Components and Technology Conference, ECTC 2013 - Las Vegas, NV, United States Duration: 28 May 2013 → 31 May 2013 |
Conference
| Conference | IEEE 63rd Electronic Components and Technology Conference, ECTC 2013 |
|---|---|
| Abbreviated title | ECTC 2013 |
| Country | United States |
| City | Las Vegas, NV |
| Period | 28/05/13 → 31/05/13 |
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Hermetic wafer level packaging of MEMS components using through silicon via and wafer to wafer bonding technologies. / Zoschke, K.; Manier, C.-A.; Wilke, M.; Jurgensen, N.; Oppermann, H.; Ruffieux, D.; Dekker, James; Heikkinen, Hannele; Piazza, S.D.; Allegato, G.; Lang, K.-D.
Proceedings: IEEE 63rd Electronic Components and Technology Conference, ECTC 2013. Institute of Electrical and Electronic Engineers IEEE, 2013. p. 1500-1507.Research output: Chapter in Book/Report/Conference proceeding › Conference article in proceedings › Scientific › peer-review
TY - GEN
T1 - Hermetic wafer level packaging of MEMS components using through silicon via and wafer to wafer bonding technologies
AU - Zoschke, K.
AU - Manier, C.-A.
AU - Wilke, M.
AU - Jurgensen, N.
AU - Oppermann, H.
AU - Ruffieux, D.
AU - Dekker, James
AU - Heikkinen, Hannele
AU - Piazza, S.D.
AU - Allegato, G.
AU - Lang, K.-D.
PY - 2013
Y1 - 2013
N2 - This paper presents the fabrication steps of a MEMS package based on silicon interposer wafers with copper filled TSVs and bonded cap wafers for hermetic sealing of resonator components. All processes were performed at 200 mm wafer level. For interposer fabrication a standard process flow including silicon blind hole etching, isolation, copper filling, wafer front side redistribution, support wafer bonding, wafer thinning, and TSV backside reveal was applied. As interposer backside metallization, appropriate I/O terminals and seal ring structures were deposited by semi-additive Au and Au+Sn electro plating. Following, getter material was deposited onto the interposer wafers which were 90 µm thick and still mounted onto carrier wafers. Subsequently, the I/O terminal pads of the interposer were stud bumped and finally more than 5000 quartz resonator components were assembled onto each interposer wafer by Au-Au direct metal bonding. The cap wafer was equipped with 200 µm deep dry etched cavities and electro plated Au seal rings around them. Finally, both cap and interposer wafers were bonded together using a wafer to wafer bonder and an adapted AuSn soldering process scheme. In a last step, the carrier wafer was removed from the former front side of the interposer wafer and wafer level testing was performed. From a total of 4824 tested devices we found that more than 75 % were sealed properly under vacuum. The getter appears to be effective leading to ~0.1 mbar equivalent air pressure and cavities without getter appear to reach residual air pressure between 1-2 mbar. The used fabrication processes and final results will be discussed detailed in this manuscript.
AB - This paper presents the fabrication steps of a MEMS package based on silicon interposer wafers with copper filled TSVs and bonded cap wafers for hermetic sealing of resonator components. All processes were performed at 200 mm wafer level. For interposer fabrication a standard process flow including silicon blind hole etching, isolation, copper filling, wafer front side redistribution, support wafer bonding, wafer thinning, and TSV backside reveal was applied. As interposer backside metallization, appropriate I/O terminals and seal ring structures were deposited by semi-additive Au and Au+Sn electro plating. Following, getter material was deposited onto the interposer wafers which were 90 µm thick and still mounted onto carrier wafers. Subsequently, the I/O terminal pads of the interposer were stud bumped and finally more than 5000 quartz resonator components were assembled onto each interposer wafer by Au-Au direct metal bonding. The cap wafer was equipped with 200 µm deep dry etched cavities and electro plated Au seal rings around them. Finally, both cap and interposer wafers were bonded together using a wafer to wafer bonder and an adapted AuSn soldering process scheme. In a last step, the carrier wafer was removed from the former front side of the interposer wafer and wafer level testing was performed. From a total of 4824 tested devices we found that more than 75 % were sealed properly under vacuum. The getter appears to be effective leading to ~0.1 mbar equivalent air pressure and cavities without getter appear to reach residual air pressure between 1-2 mbar. The used fabrication processes and final results will be discussed detailed in this manuscript.
U2 - 10.1109/ECTC.2013.6575770
DO - 10.1109/ECTC.2013.6575770
M3 - Conference article in proceedings
SN - 978-1-4799-0233-0
SP - 1500
EP - 1507
BT - Proceedings
PB - Institute of Electrical and Electronic Engineers IEEE
ER -