Hermetic wafer level packaging of MEMS components using through silicon via and wafer to wafer bonding technologies

K. Zoschke, C.-A. Manier, M. Wilke, N. Jürgensen, H. Oppermann, D. Ruffieux, James Dekker, Hannele Heikkinen, S. Dalla Piazza, G. Allegato, K.-D. Lang

    Research output: Chapter in Book/Report/Conference proceedingConference article in proceedingsScientificpeer-review

    22 Citations (Scopus)

    Abstract

    This paper presents the fabrication steps of a MEMS package based on silicon interposer wafers with copper filled TSVs and bonded cap wafers for hermetic sealing of resonator components. All processes were performed at 200 mm wafer level. For interposer fabrication a standard process flow including silicon blind hole etching, isolation, copper filling, wafer front side redistribution, support wafer bonding, wafer thinning, and TSV backside reveal was applied. As interposer backside metallization, appropriate I/O terminals and seal ring structures were deposited by semi-additive Au and Au+Sn electro plating. Following, getter material was deposited onto the interposer wafers which were 90 µm thick and still mounted onto carrier wafers. Subsequently, the I/O terminal pads of the interposer were stud bumped and finally more than 5000 quartz resonator components were assembled onto each interposer wafer by Au-Au direct metal bonding. The cap wafer was equipped with 200 µm deep dry etched cavities and electro plated Au seal rings around them. Finally, both cap and interposer wafers were bonded together using a wafer to wafer bonder and an adapted AuSn soldering process scheme. In a last step, the carrier wafer was removed from the former front side of the interposer wafer and wafer level testing was performed. From a total of 4824 tested devices we found that more than 75 % were sealed properly under vacuum. The getter appears to be effective leading to ~0.1 mbar equivalent air pressure and cavities without getter appear to reach residual air pressure between 1-2 mbar. The used fabrication processes and final results will be discussed detailed in this manuscript.
    Original languageEnglish
    Title of host publicationIEEE 63rd Electronic Components and Technology Conference, ECTC 2013
    PublisherIEEE Institute of Electrical and Electronic Engineers
    Pages1500-1507
    ISBN (Electronic)978-1-4799-0232-3
    ISBN (Print)978-1-4799-0233-0
    DOIs
    Publication statusPublished - 2013
    MoE publication typeA4 Article in a conference publication
    EventIEEE 63rd Electronic Components and Technology Conference, ECTC 2013 - Las Vegas, NV, United States
    Duration: 28 May 201331 May 2013

    Publication series

    SeriesElectronic Components and Technology Conference (ECTC)
    Volume63
    ISSN0569-5503

    Conference

    ConferenceIEEE 63rd Electronic Components and Technology Conference, ECTC 2013
    Abbreviated titleECTC 2013
    Country/TerritoryUnited States
    CityLas Vegas, NV
    Period28/05/1331/05/13

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