High-bandwidth on-chip communication architecture for general purpose computing

Current on-chip communication architectures fail to support fine-grained general purpose computing due to lack of bandwidth, scalability and efficient synchronization schemes. In this paper we attack these problems by describing a double acyclic sparse mesh communication architecture featuring constant degree switches, fixed length intercommunication wiring, chip-wide synchronization wave scheme, and linear bandwidth scaling mechanism, being a part of our previously outlined ECLIPSE computing architecture. The network architecture is compared against the traditional mesh approach with simulations and VHDL modeling and shown to provide much higher bandwidth in random communication needed to realize general purpose high-performance computing engine while the silicon area overhead of the communication architecture remains at acceptable level. The performance of the architecture is verified with real parallel benchmarks.