Current on-chip communication architectures fail to support fine-grained general purpose computing due to lack of bandwidth, scalability and efficient synchronization schemes. In this paper we attack these problems by describing a double acyclic sparse mesh communication architecture featuring constant degree switches, fixed length intercommunication wiring, chip-wide synchronization wave scheme, and linear bandwidth scaling mechanism, being a part of our previously outlined ECLIPSE computing architecture. The network architecture is compared against the traditional mesh approach with simulations and VHDL modeling and shown to provide much higher bandwidth in random communication needed to realize general purpose high-performance computing engine while the silicon area overhead of the communication architecture remains at acceptable level. The performance of the architecture is verified with real parallel benchmarks.
|Title of host publication||Proceedings 2005 // WMSCI 2005|
|Subtitle of host publication||the 9th World Multiconference on Systemics, Cybernetics and Informatics|
|Publisher||International institute of informatics and systemics|
|ISBN (Print)||980-65-6052-3, 980-65-6056-6|
|Publication status||Published - 2005|
|MoE publication type||A4 Article in a conference publication|
|Event||9th World Multiconference on Systemics, Cybernetics and Informatics, WMSCI 2005 - Orlando, United States|
Duration: 10 Jul 2005 → 13 Jul 2005
Conference number: 9
|Conference||9th World Multiconference on Systemics, Cybernetics and Informatics, WMSCI 2005|
|Abbreviated title||WMSCI 2005|
|Period||10/07/05 → 13/07/05|
- On-chip communication
- general purpose parallel computing
Forsell, M., & Leppänen, V. (2005). High-bandwidth on-chip communication architecture for general purpose computing. In Proceedings 2005 // WMSCI 2005: the 9th World Multiconference on Systemics, Cybernetics and Informatics (Vol. 4, pp. 1-6). International institute of informatics and systemics.