Abstract
Full system electricity intake from the wall socket is
important for understanding and budgeting the power
consumption of large scale data centers. Measuring full
system power, however, requires extra instrumentation
with external physical devices, which is not only
cumbersome, but also expensive and time consuming. To
tackle this problem, in this paper, we propose to model
wall socket power from processor package power obtained
from the running average power limit (RAPL) interface,
which is available on the latest Intel processors. Our
experimental results demonstrate a strong correlation
between RAPL package power and wall socket power
consumption. Based on the observations, we propose an
empirical power model to predict the full system power.
We verify the model using multiple synthetic benchmarks
(Stress-ng, STREAM), high energy physics benchmark
(ParFullCMS), and non-trivial application benchmarks
(Parsec). Experimental results show that the prediction
model achieves good accuracy, which is maximum 5.6Â %
error rate.
Original language | English |
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Pages (from-to) | 207-214 |
Number of pages | 8 |
Journal | Computer Science: Research and Development |
Volume | 31 |
Issue number | 4 |
DOIs | |
Publication status | Published - 1 Nov 2016 |
MoE publication type | A1 Journal article-refereed |
Keywords
- energy efficiency
- HPC
- power modeling
- RAPL