HPPC 2007: Workshop on Highly Parallel Processing on a Chip

Martti Forsell, Jesper Larsson Träff

Research output: Chapter in Book/Report/Conference proceedingChapter or book articleScientific

Abstract

Technological developments are bringing parallel computing back into the lime-light after some years of absence from the stage of mainstream computing and computer science between the early 1990ties and early 2000s. The driving forces behind this return are mainly technological: increasing transistor densities along with hot chips, leaky transistors, and slow wires - coupled with the infeasibility of extracting significantly more ILP at execution time - make it unlikely that the increase in single processor performance can continue the exponential growth that has been sustained over the last 30 years. To satisfy the needs for application performance, ma jor processor manufacturers are instead counting on doubling the number of processor cores per chip every second year, in accordance with the original formulation of Moore's law. We are therefore on the brink of entering a new era of highly parallel processing on a chip. However, many fundamental unresolved hardware and software issues remain that may make the transition slower and more painful than is optimistically expected from many sides. Among the most important such issues are convergence on an abstract architecture, programming model, and language to easily and efficiently realize the performance potential inherent in the technological developments. The Workshop on Highly Paral lel Processing on a Chip (HPPC) aims to be a forum for discussing such fundamental issues. It is open to all aspects of existing and emerging/envisaged multi-core (by which is meant: many-core) processors with a significant amount of parallelism, especially to considerations on novel paradigms and models and the related architectural and linguistic support. To be able to relate to the parallel processing community at large, which we consider essential, the workshop has been organized in conjunction with EuroPar, the main European (but international) conference on all aspects of parallel processing. The Call-for-papers for the HPPC workshop was launched early in the year 2007, and at the passing of the submission deadline we had received 20 submissions, which were of good quality and generally relevant to the theme of the workshop. The papers were swiftly and expertly reviewed by the program committee, most of them receiving four qualified reviews. The program chairs thank the whole of the program committee for the time and expertise they put into the reviewing work, and for getting it all done within the rather strict time limit. Final decision on acceptance was made by the program chairs based on the recommendations from the program committee. Being a(n extended) half-day event, there was room for accepting only 6 of the contributions, resulting in an acceptance ratio of about 30%. Five of the 6 accepted contributions were presented at the workshop (the paper not presented is as a matter of principle not included in these proceedings), together with two forward looking invited talks by Uzi Vishkin and Thomas Sterling on realizing a PRAM-on-a-chip vision and societies of cores and their computing culture. This post-workshop proceedings includes the final versions of the presented HPPC papers, taking the feedback from reviewers and workshop audience into account. In addition, the extended abstracts of the two invited talks by Uzi Vishkin and Thomas Sterling have also been included in the proceedings. The program chairs sincerely thank the EuroPar organization for providing the opportunity to arrange the HPPC workshop in conjunction with the EuroPar 2007 conference. We also warmly thank our sponsors VTT and EuroPar for financial support, which made it possible to invite Uzi Vishkin and Thomas Sterling, both of whom we also sincerely thank for accepting our invitation to come and speak. Finally, we thank all attendees at the workshop, who contributed to a lively day, and hope they too found something of interest in the workshop. Based on the mostly positive feedback the program chairs and organizers plan to continue the HPPC workshop in conjunction with EuroPar 2008.
Original languageEnglish
Title of host publicationEuro-Par 2007 Workshops
Subtitle of host publicationParallel Processing
EditorsLuc Bougé, Martti Forsell, Jesper Larsson Träff, Achim Streit, Wolfgang Ziegler, Michael Alexander, Stephen Childs
Place of PublicationGermany
PublisherSpringer
Pages3-58
ISBN (Electronic)978-3-540-78474-6
ISBN (Print)978-3-540-78472-2
DOIs
Publication statusPublished - 2008
MoE publication typeB2 Part of a book or another research book
EventEuro-Par 2007 Workshops - Rennes, France
Duration: 28 Aug 200731 Aug 2007

Publication series

NameIFIP Advances in Information and Communication Technology
PublisherSpringer
ISSN (Print)0302-9743
ISSN (Electronic)1571-5736

Conference

ConferenceEuro-Par 2007 Workshops
CountryFrance
CityRennes
Period28/08/0731/08/07

Fingerprint

Processing
Transistors
Feedback
Inductive logic programming (ILP)
Parallel processing systems
Linguistics
Lime
Computer science
Wire
Hardware

Cite this

Forsell, M., & Larsson Träff, J. (2008). HPPC 2007: Workshop on Highly Parallel Processing on a Chip. In L. Bougé, M. Forsell, J. Larsson Träff, A. Streit, W. Ziegler, M. Alexander, & S. Childs (Eds.), Euro-Par 2007 Workshops: Parallel Processing (pp. 3-58). Germany: Springer. Lecture Notes in Computer Science, Vol.. 4854 https://doi.org/10.1007/978-3-540-78474-6_1
Forsell, Martti ; Larsson Träff, Jesper. / HPPC 2007: Workshop on Highly Parallel Processing on a Chip. Euro-Par 2007 Workshops: Parallel Processing. editor / Luc Bougé ; Martti Forsell ; Jesper Larsson Träff ; Achim Streit ; Wolfgang Ziegler ; Michael Alexander ; Stephen Childs. Germany : Springer, 2008. pp. 3-58 (Lecture Notes in Computer Science, Vol. 4854).
@inbook{c53b0bb2a0834c8e8a25c311a3e583d2,
title = "HPPC 2007: Workshop on Highly Parallel Processing on a Chip",
abstract = "Technological developments are bringing parallel computing back into the lime-light after some years of absence from the stage of mainstream computing and computer science between the early 1990ties and early 2000s. The driving forces behind this return are mainly technological: increasing transistor densities along with hot chips, leaky transistors, and slow wires - coupled with the infeasibility of extracting significantly more ILP at execution time - make it unlikely that the increase in single processor performance can continue the exponential growth that has been sustained over the last 30 years. To satisfy the needs for application performance, ma jor processor manufacturers are instead counting on doubling the number of processor cores per chip every second year, in accordance with the original formulation of Moore's law. We are therefore on the brink of entering a new era of highly parallel processing on a chip. However, many fundamental unresolved hardware and software issues remain that may make the transition slower and more painful than is optimistically expected from many sides. Among the most important such issues are convergence on an abstract architecture, programming model, and language to easily and efficiently realize the performance potential inherent in the technological developments. The Workshop on Highly Paral lel Processing on a Chip (HPPC) aims to be a forum for discussing such fundamental issues. It is open to all aspects of existing and emerging/envisaged multi-core (by which is meant: many-core) processors with a significant amount of parallelism, especially to considerations on novel paradigms and models and the related architectural and linguistic support. To be able to relate to the parallel processing community at large, which we consider essential, the workshop has been organized in conjunction with EuroPar, the main European (but international) conference on all aspects of parallel processing. The Call-for-papers for the HPPC workshop was launched early in the year 2007, and at the passing of the submission deadline we had received 20 submissions, which were of good quality and generally relevant to the theme of the workshop. The papers were swiftly and expertly reviewed by the program committee, most of them receiving four qualified reviews. The program chairs thank the whole of the program committee for the time and expertise they put into the reviewing work, and for getting it all done within the rather strict time limit. Final decision on acceptance was made by the program chairs based on the recommendations from the program committee. Being a(n extended) half-day event, there was room for accepting only 6 of the contributions, resulting in an acceptance ratio of about 30{\%}. Five of the 6 accepted contributions were presented at the workshop (the paper not presented is as a matter of principle not included in these proceedings), together with two forward looking invited talks by Uzi Vishkin and Thomas Sterling on realizing a PRAM-on-a-chip vision and societies of cores and their computing culture. This post-workshop proceedings includes the final versions of the presented HPPC papers, taking the feedback from reviewers and workshop audience into account. In addition, the extended abstracts of the two invited talks by Uzi Vishkin and Thomas Sterling have also been included in the proceedings. The program chairs sincerely thank the EuroPar organization for providing the opportunity to arrange the HPPC workshop in conjunction with the EuroPar 2007 conference. We also warmly thank our sponsors VTT and EuroPar for financial support, which made it possible to invite Uzi Vishkin and Thomas Sterling, both of whom we also sincerely thank for accepting our invitation to come and speak. Finally, we thank all attendees at the workshop, who contributed to a lively day, and hope they too found something of interest in the workshop. Based on the mostly positive feedback the program chairs and organizers plan to continue the HPPC workshop in conjunction with EuroPar 2008.",
author = "Martti Forsell and {Larsson Tr{\"a}ff}, Jesper",
year = "2008",
doi = "10.1007/978-3-540-78474-6_1",
language = "English",
isbn = "978-3-540-78472-2",
series = "IFIP Advances in Information and Communication Technology",
publisher = "Springer",
pages = "3--58",
editor = "Luc Boug{\'e} and Martti Forsell and {Larsson Tr{\"a}ff}, Jesper and Achim Streit and Wolfgang Ziegler and Michael Alexander and Stephen Childs",
booktitle = "Euro-Par 2007 Workshops",
address = "Germany",

}

Forsell, M & Larsson Träff, J 2008, HPPC 2007: Workshop on Highly Parallel Processing on a Chip. in L Bougé, M Forsell, J Larsson Träff, A Streit, W Ziegler, M Alexander & S Childs (eds), Euro-Par 2007 Workshops: Parallel Processing. Springer, Germany, Lecture Notes in Computer Science, vol. 4854, pp. 3-58, Euro-Par 2007 Workshops, Rennes, France, 28/08/07. https://doi.org/10.1007/978-3-540-78474-6_1

HPPC 2007: Workshop on Highly Parallel Processing on a Chip. / Forsell, Martti; Larsson Träff, Jesper.

Euro-Par 2007 Workshops: Parallel Processing. ed. / Luc Bougé; Martti Forsell; Jesper Larsson Träff; Achim Streit; Wolfgang Ziegler; Michael Alexander; Stephen Childs. Germany : Springer, 2008. p. 3-58 (Lecture Notes in Computer Science, Vol. 4854).

Research output: Chapter in Book/Report/Conference proceedingChapter or book articleScientific

TY - CHAP

T1 - HPPC 2007: Workshop on Highly Parallel Processing on a Chip

AU - Forsell, Martti

AU - Larsson Träff, Jesper

PY - 2008

Y1 - 2008

N2 - Technological developments are bringing parallel computing back into the lime-light after some years of absence from the stage of mainstream computing and computer science between the early 1990ties and early 2000s. The driving forces behind this return are mainly technological: increasing transistor densities along with hot chips, leaky transistors, and slow wires - coupled with the infeasibility of extracting significantly more ILP at execution time - make it unlikely that the increase in single processor performance can continue the exponential growth that has been sustained over the last 30 years. To satisfy the needs for application performance, ma jor processor manufacturers are instead counting on doubling the number of processor cores per chip every second year, in accordance with the original formulation of Moore's law. We are therefore on the brink of entering a new era of highly parallel processing on a chip. However, many fundamental unresolved hardware and software issues remain that may make the transition slower and more painful than is optimistically expected from many sides. Among the most important such issues are convergence on an abstract architecture, programming model, and language to easily and efficiently realize the performance potential inherent in the technological developments. The Workshop on Highly Paral lel Processing on a Chip (HPPC) aims to be a forum for discussing such fundamental issues. It is open to all aspects of existing and emerging/envisaged multi-core (by which is meant: many-core) processors with a significant amount of parallelism, especially to considerations on novel paradigms and models and the related architectural and linguistic support. To be able to relate to the parallel processing community at large, which we consider essential, the workshop has been organized in conjunction with EuroPar, the main European (but international) conference on all aspects of parallel processing. The Call-for-papers for the HPPC workshop was launched early in the year 2007, and at the passing of the submission deadline we had received 20 submissions, which were of good quality and generally relevant to the theme of the workshop. The papers were swiftly and expertly reviewed by the program committee, most of them receiving four qualified reviews. The program chairs thank the whole of the program committee for the time and expertise they put into the reviewing work, and for getting it all done within the rather strict time limit. Final decision on acceptance was made by the program chairs based on the recommendations from the program committee. Being a(n extended) half-day event, there was room for accepting only 6 of the contributions, resulting in an acceptance ratio of about 30%. Five of the 6 accepted contributions were presented at the workshop (the paper not presented is as a matter of principle not included in these proceedings), together with two forward looking invited talks by Uzi Vishkin and Thomas Sterling on realizing a PRAM-on-a-chip vision and societies of cores and their computing culture. This post-workshop proceedings includes the final versions of the presented HPPC papers, taking the feedback from reviewers and workshop audience into account. In addition, the extended abstracts of the two invited talks by Uzi Vishkin and Thomas Sterling have also been included in the proceedings. The program chairs sincerely thank the EuroPar organization for providing the opportunity to arrange the HPPC workshop in conjunction with the EuroPar 2007 conference. We also warmly thank our sponsors VTT and EuroPar for financial support, which made it possible to invite Uzi Vishkin and Thomas Sterling, both of whom we also sincerely thank for accepting our invitation to come and speak. Finally, we thank all attendees at the workshop, who contributed to a lively day, and hope they too found something of interest in the workshop. Based on the mostly positive feedback the program chairs and organizers plan to continue the HPPC workshop in conjunction with EuroPar 2008.

AB - Technological developments are bringing parallel computing back into the lime-light after some years of absence from the stage of mainstream computing and computer science between the early 1990ties and early 2000s. The driving forces behind this return are mainly technological: increasing transistor densities along with hot chips, leaky transistors, and slow wires - coupled with the infeasibility of extracting significantly more ILP at execution time - make it unlikely that the increase in single processor performance can continue the exponential growth that has been sustained over the last 30 years. To satisfy the needs for application performance, ma jor processor manufacturers are instead counting on doubling the number of processor cores per chip every second year, in accordance with the original formulation of Moore's law. We are therefore on the brink of entering a new era of highly parallel processing on a chip. However, many fundamental unresolved hardware and software issues remain that may make the transition slower and more painful than is optimistically expected from many sides. Among the most important such issues are convergence on an abstract architecture, programming model, and language to easily and efficiently realize the performance potential inherent in the technological developments. The Workshop on Highly Paral lel Processing on a Chip (HPPC) aims to be a forum for discussing such fundamental issues. It is open to all aspects of existing and emerging/envisaged multi-core (by which is meant: many-core) processors with a significant amount of parallelism, especially to considerations on novel paradigms and models and the related architectural and linguistic support. To be able to relate to the parallel processing community at large, which we consider essential, the workshop has been organized in conjunction with EuroPar, the main European (but international) conference on all aspects of parallel processing. The Call-for-papers for the HPPC workshop was launched early in the year 2007, and at the passing of the submission deadline we had received 20 submissions, which were of good quality and generally relevant to the theme of the workshop. The papers were swiftly and expertly reviewed by the program committee, most of them receiving four qualified reviews. The program chairs thank the whole of the program committee for the time and expertise they put into the reviewing work, and for getting it all done within the rather strict time limit. Final decision on acceptance was made by the program chairs based on the recommendations from the program committee. Being a(n extended) half-day event, there was room for accepting only 6 of the contributions, resulting in an acceptance ratio of about 30%. Five of the 6 accepted contributions were presented at the workshop (the paper not presented is as a matter of principle not included in these proceedings), together with two forward looking invited talks by Uzi Vishkin and Thomas Sterling on realizing a PRAM-on-a-chip vision and societies of cores and their computing culture. This post-workshop proceedings includes the final versions of the presented HPPC papers, taking the feedback from reviewers and workshop audience into account. In addition, the extended abstracts of the two invited talks by Uzi Vishkin and Thomas Sterling have also been included in the proceedings. The program chairs sincerely thank the EuroPar organization for providing the opportunity to arrange the HPPC workshop in conjunction with the EuroPar 2007 conference. We also warmly thank our sponsors VTT and EuroPar for financial support, which made it possible to invite Uzi Vishkin and Thomas Sterling, both of whom we also sincerely thank for accepting our invitation to come and speak. Finally, we thank all attendees at the workshop, who contributed to a lively day, and hope they too found something of interest in the workshop. Based on the mostly positive feedback the program chairs and organizers plan to continue the HPPC workshop in conjunction with EuroPar 2008.

U2 - 10.1007/978-3-540-78474-6_1

DO - 10.1007/978-3-540-78474-6_1

M3 - Chapter or book article

SN - 978-3-540-78472-2

T3 - IFIP Advances in Information and Communication Technology

SP - 3

EP - 58

BT - Euro-Par 2007 Workshops

A2 - Bougé, Luc

A2 - Forsell, Martti

A2 - Larsson Träff, Jesper

A2 - Streit, Achim

A2 - Ziegler, Wolfgang

A2 - Alexander, Michael

A2 - Childs, Stephen

PB - Springer

CY - Germany

ER -

Forsell M, Larsson Träff J. HPPC 2007: Workshop on Highly Parallel Processing on a Chip. In Bougé L, Forsell M, Larsson Träff J, Streit A, Ziegler W, Alexander M, Childs S, editors, Euro-Par 2007 Workshops: Parallel Processing. Germany: Springer. 2008. p. 3-58. (Lecture Notes in Computer Science, Vol. 4854). https://doi.org/10.1007/978-3-540-78474-6_1