HPPC 2009: 3rd Workshop on Highly Parallel Processing on a Chip

Martti Forsell, Jesper Larsson Träff

    Research output: Chapter in Book/Report/Conference proceedingChapter or book articleScientificpeer-review

    Abstract

    To counter the relative decline in traditional, single-processor performance, architectures with significant on-chip parallelism for special and general-purpose computation have been marketed in the past few years with various degrees of success. Although the shift toward (general-purpose) parallel processing is inevitable and generally accepted, the road to travel is still essentially unclear - perhaps even unknown, as witnessed by the many different architectural proposals and products by both large and smaller vendors, the usual hype, as well as research projects in many different directions.
    Original languageEnglish
    Title of host publicationEuro-Par 2009 – Parallel Processing Workshops
    EditorsHai-Xiang Lin, Michael Alexander, Martti Forsell, Andreas Knüpfer, Radu Prodan, Leonel Sousa, Achim Streit
    Place of PublicationBerlin Heidelberg
    PublisherSpringer
    Pages3-5
    ISBN (Electronic)978-3-642-14122-5
    ISBN (Print)978-3-642-14121-8, 3-642-14121-8
    DOIs
    Publication statusPublished - 2010
    MoE publication typeA3 Part of a book or another research book
    EventEuro-Par 2009
    : Parallel Processing Workshops
    - Delft, Netherlands
    Duration: 25 Aug 200928 Aug 2009

    Workshop

    WorkshopEuro-Par 2009
    CountryNetherlands
    CityDelft
    Period25/08/0928/08/09

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    Cite this

    Forsell, M., & Larsson Träff, J. (2010). HPPC 2009: 3rd Workshop on Highly Parallel Processing on a Chip. In H-X. Lin, M. Alexander, M. Forsell, A. Knüpfer, R. Prodan, L. Sousa, & A. Streit (Eds.), Euro-Par 2009 – Parallel Processing Workshops (pp. 3-5). Springer. https://doi.org/10.1007/978-3-642-14122-5_1