HPPC 2010: 5th Workshop on highly parallel processing on a chip

Martti Forsell, J.L. Träff

Research output: Chapter in Book/Report/Conference proceedingConference article in proceedingsScientific

Abstract

Despite the processor industry having more or less successfully invested already 10 years to develop better and increasingly parallel multicore architectures, both software community and educational institutions appear still to rely on the sequential computing paradigm as the primary mechanism for expressing the (very often originally inherently parallel) functionality, especially in the arena of general purpose computing. In that respect, parallel programming has remained a hobby of highly educated specialists and is still too often being considered as too difficult for the average programmer. Excuses are various: lack of education, lack of suitable easy-to-use tools, too architecture-dependent mechanisms, huge existing base of sequential legacy code, steep learning curves, and inefficient architectures. It is important for the scientific community to analyze the situation and understand whether the problem is with hardware architectures, software development tools and practices, or both. Although we would be tempted to answer this question (and actually try to do so elsewhere), there is strong need for wider academic discussion on these topics and presentation of research results in scientific workshops and conferences.
Original languageEnglish
Title of host publicationProceedings
Subtitle of host publicationParallel Processing Workshops, Euro-Par 2011
EditorsMichael Alexander, Pasqua D’Ambra, Adam Belloum, George Bosilca, Mario Cannataro, Marco Danelutto, Beniamino Di Martino, Michael Gerndt, Emmanuel Jeannot, Raymond Namyst, Jean Roman, Stephen L. Scott, Jesper Larsson Traff, Geoffroy Vallée, Josef Weidendorfer
Place of PublicationBerlin, Heidelberg
PublisherSpringer
Pages245-247
ISBN (Electronic)978-3-642-29737-3
ISBN (Print)978-3-642-29736-6
DOIs
Publication statusPublished - 2012
MoE publication typeB3 Non-refereed article in conference proceedings
EventEuro-Par 2011: Parallel Processing Workshops: PI, CGWS, HeteroPar, HiBB, HPCVirt, HPPC, HPSS, MDGS, ProPer, Resilience, UCHPC, VHPC - Bordeaux, France
Duration: 29 Aug 20112 Sep 2011

Publication series

SeriesLecture Notes in Computer Science
Volume7155
ISSN0302-9743

Conference

ConferenceEuro-Par 2011: Parallel Processing Workshops: PI, CGWS, HeteroPar, HiBB, HPCVirt, HPPC, HPSS, MDGS, ProPer, Resilience, UCHPC, VHPC
CountryFrance
CityBordeaux
Period29/08/112/09/11

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Parallel programming
Software architecture
Processing
Computer hardware
Software engineering
Education
Industry

Cite this

Forsell, M., & Träff, J. L. (2012). HPPC 2010: 5th Workshop on highly parallel processing on a chip. In M. Alexander, P. D’Ambra, A. Belloum, G. Bosilca, M. Cannataro, M. Danelutto, B. Di Martino, M. Gerndt, E. Jeannot, R. Namyst, J. Roman, S. L. Scott, J. Larsson Traff, G. Vallée, ... J. Weidendorfer (Eds.), Proceedings: Parallel Processing Workshops, Euro-Par 2011 (pp. 245-247). Berlin, Heidelberg: Springer. Lecture Notes in Computer Science, Vol.. 7155 https://doi.org/10.1007/978-3-642-29737-3_28
Forsell, Martti ; Träff, J.L. / HPPC 2010 : 5th Workshop on highly parallel processing on a chip. Proceedings: Parallel Processing Workshops, Euro-Par 2011. editor / Michael Alexander ; Pasqua D’Ambra ; Adam Belloum ; George Bosilca ; Mario Cannataro ; Marco Danelutto ; Beniamino Di Martino ; Michael Gerndt ; Emmanuel Jeannot ; Raymond Namyst ; Jean Roman ; Stephen L. Scott ; Jesper Larsson Traff ; Geoffroy Vallée ; Josef Weidendorfer. Berlin, Heidelberg : Springer, 2012. pp. 245-247 (Lecture Notes in Computer Science, Vol. 7155).
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Forsell, M & Träff, JL 2012, HPPC 2010: 5th Workshop on highly parallel processing on a chip. in M Alexander, P D’Ambra, A Belloum, G Bosilca, M Cannataro, M Danelutto, B Di Martino, M Gerndt, E Jeannot, R Namyst, J Roman, SL Scott, J Larsson Traff, G Vallée & J Weidendorfer (eds), Proceedings: Parallel Processing Workshops, Euro-Par 2011. Springer, Berlin, Heidelberg, Lecture Notes in Computer Science, vol. 7155, pp. 245-247, Euro-Par 2011: Parallel Processing Workshops: PI, CGWS, HeteroPar, HiBB, HPCVirt, HPPC, HPSS, MDGS, ProPer, Resilience, UCHPC, VHPC, Bordeaux, France, 29/08/11. https://doi.org/10.1007/978-3-642-29737-3_28

HPPC 2010 : 5th Workshop on highly parallel processing on a chip. / Forsell, Martti; Träff, J.L.

Proceedings: Parallel Processing Workshops, Euro-Par 2011. ed. / Michael Alexander; Pasqua D’Ambra; Adam Belloum; George Bosilca; Mario Cannataro; Marco Danelutto; Beniamino Di Martino; Michael Gerndt; Emmanuel Jeannot; Raymond Namyst; Jean Roman; Stephen L. Scott; Jesper Larsson Traff; Geoffroy Vallée; Josef Weidendorfer. Berlin, Heidelberg : Springer, 2012. p. 245-247 (Lecture Notes in Computer Science, Vol. 7155).

Research output: Chapter in Book/Report/Conference proceedingConference article in proceedingsScientific

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AB - Despite the processor industry having more or less successfully invested already 10 years to develop better and increasingly parallel multicore architectures, both software community and educational institutions appear still to rely on the sequential computing paradigm as the primary mechanism for expressing the (very often originally inherently parallel) functionality, especially in the arena of general purpose computing. In that respect, parallel programming has remained a hobby of highly educated specialists and is still too often being considered as too difficult for the average programmer. Excuses are various: lack of education, lack of suitable easy-to-use tools, too architecture-dependent mechanisms, huge existing base of sequential legacy code, steep learning curves, and inefficient architectures. It is important for the scientific community to analyze the situation and understand whether the problem is with hardware architectures, software development tools and practices, or both. Although we would be tempted to answer this question (and actually try to do so elsewhere), there is strong need for wider academic discussion on these topics and presentation of research results in scientific workshops and conferences.

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A2 - Namyst, Raymond

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A2 - Vallée, Geoffroy

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PB - Springer

CY - Berlin, Heidelberg

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Forsell M, Träff JL. HPPC 2010: 5th Workshop on highly parallel processing on a chip. In Alexander M, D’Ambra P, Belloum A, Bosilca G, Cannataro M, Danelutto M, Di Martino B, Gerndt M, Jeannot E, Namyst R, Roman J, Scott SL, Larsson Traff J, Vallée G, Weidendorfer J, editors, Proceedings: Parallel Processing Workshops, Euro-Par 2011. Berlin, Heidelberg: Springer. 2012. p. 245-247. (Lecture Notes in Computer Science, Vol. 7155). https://doi.org/10.1007/978-3-642-29737-3_28