HV NMOS transistor for IC/MEMS integration on SOI

Roope Jansson (Corresponding Author), Hannu Ronkainen, Jyrki Kiihamäki, Joni Mellin

Research output: Contribution to journalArticleScientificpeer-review

1 Citation (Scopus)

Abstract

This paper describes the procedure of creating HV NMOS transistor for IC/MEMS integration on thick SOI wafers. The result of this kind of integration is essential for many next-generation applications. High bias voltages are needed with MEMS devices to create more complex entities on a single chip. SOI wafers are ideal for this kind of integration as MEMS devices can be fabricated using buried oxide layer. Thick SOI also provides a substrate that can be used for CMOS processes with little or no modifications. Two different SOI were used as well as bulk wafers to verify the results. The SOI layer was either uniformly doped or it had a buried p+ layer. The SOI had an 8µm thick device layer with 1µm thick buried oxide. Critical layout parameters are identified and test structures have been designed to study the layout effects. Properties of the HV NMOS transistor for these different substrates and for different layouts are compared. HV NMOS transistor has been successfully fabricated for IC/MEMS integration on SOI.
Original languageEnglish
Pages (from-to)110 - 112
Number of pages3
JournalPhysica Scripta
VolumeT114
DOIs
Publication statusPublished - 2004
MoE publication typeA1 Journal article-refereed
Event20th Nordic Semiconductor Meeting, NSM20 - Tampere, Finland
Duration: 25 Aug 200327 Aug 2003

Fingerprint

SOI (semiconductors)
Micro-electro-mechanical Systems
microelectromechanical systems
transistors
Wafer
Layout
Oxides
layouts
Substrate
wafers
Chip
Voltage
Verify
oxides
CMOS
chips
electric potential

Cite this

Jansson, Roope ; Ronkainen, Hannu ; Kiihamäki, Jyrki ; Mellin, Joni. / HV NMOS transistor for IC/MEMS integration on SOI. In: Physica Scripta. 2004 ; Vol. T114. pp. 110 - 112.
@article{6d29cc2abb47481da528e753074e654d,
title = "HV NMOS transistor for IC/MEMS integration on SOI",
abstract = "This paper describes the procedure of creating HV NMOS transistor for IC/MEMS integration on thick SOI wafers. The result of this kind of integration is essential for many next-generation applications. High bias voltages are needed with MEMS devices to create more complex entities on a single chip. SOI wafers are ideal for this kind of integration as MEMS devices can be fabricated using buried oxide layer. Thick SOI also provides a substrate that can be used for CMOS processes with little or no modifications. Two different SOI were used as well as bulk wafers to verify the results. The SOI layer was either uniformly doped or it had a buried p+ layer. The SOI had an 8µm thick device layer with 1µm thick buried oxide. Critical layout parameters are identified and test structures have been designed to study the layout effects. Properties of the HV NMOS transistor for these different substrates and for different layouts are compared. HV NMOS transistor has been successfully fabricated for IC/MEMS integration on SOI.",
author = "Roope Jansson and Hannu Ronkainen and Jyrki Kiiham{\"a}ki and Joni Mellin",
year = "2004",
doi = "10.1088/0031-8949/2004/T114/027",
language = "English",
volume = "T114",
pages = "110 -- 112",
journal = "Physica Scripta",
issn = "0031-8949",
publisher = "Institute of Physics IOP",

}

HV NMOS transistor for IC/MEMS integration on SOI. / Jansson, Roope (Corresponding Author); Ronkainen, Hannu; Kiihamäki, Jyrki; Mellin, Joni.

In: Physica Scripta, Vol. T114, 2004, p. 110 - 112.

Research output: Contribution to journalArticleScientificpeer-review

TY - JOUR

T1 - HV NMOS transistor for IC/MEMS integration on SOI

AU - Jansson, Roope

AU - Ronkainen, Hannu

AU - Kiihamäki, Jyrki

AU - Mellin, Joni

PY - 2004

Y1 - 2004

N2 - This paper describes the procedure of creating HV NMOS transistor for IC/MEMS integration on thick SOI wafers. The result of this kind of integration is essential for many next-generation applications. High bias voltages are needed with MEMS devices to create more complex entities on a single chip. SOI wafers are ideal for this kind of integration as MEMS devices can be fabricated using buried oxide layer. Thick SOI also provides a substrate that can be used for CMOS processes with little or no modifications. Two different SOI were used as well as bulk wafers to verify the results. The SOI layer was either uniformly doped or it had a buried p+ layer. The SOI had an 8µm thick device layer with 1µm thick buried oxide. Critical layout parameters are identified and test structures have been designed to study the layout effects. Properties of the HV NMOS transistor for these different substrates and for different layouts are compared. HV NMOS transistor has been successfully fabricated for IC/MEMS integration on SOI.

AB - This paper describes the procedure of creating HV NMOS transistor for IC/MEMS integration on thick SOI wafers. The result of this kind of integration is essential for many next-generation applications. High bias voltages are needed with MEMS devices to create more complex entities on a single chip. SOI wafers are ideal for this kind of integration as MEMS devices can be fabricated using buried oxide layer. Thick SOI also provides a substrate that can be used for CMOS processes with little or no modifications. Two different SOI were used as well as bulk wafers to verify the results. The SOI layer was either uniformly doped or it had a buried p+ layer. The SOI had an 8µm thick device layer with 1µm thick buried oxide. Critical layout parameters are identified and test structures have been designed to study the layout effects. Properties of the HV NMOS transistor for these different substrates and for different layouts are compared. HV NMOS transistor has been successfully fabricated for IC/MEMS integration on SOI.

U2 - 10.1088/0031-8949/2004/T114/027

DO - 10.1088/0031-8949/2004/T114/027

M3 - Article

VL - T114

SP - 110

EP - 112

JO - Physica Scripta

JF - Physica Scripta

SN - 0031-8949

ER -