Abstract
This paper describes the procedure of creating HV NMOS transistor for
IC/MEMS integration on thick SOI wafers. The result of this kind of
integration is essential for many next-generation applications. High
bias voltages are needed with MEMS devices to create more complex
entities on a single chip. SOI wafers are ideal for this kind of
integration as MEMS devices can be fabricated using buried oxide layer.
Thick SOI also provides a substrate that can be used for CMOS processes
with little or no modifications. Two different SOI were used as well as
bulk wafers to verify the results. The SOI layer was either uniformly
doped or it had a buried p+ layer. The SOI had an 8µm thick device layer
with 1µm thick buried oxide. Critical layout parameters are identified
and test structures have been designed to study the layout effects.
Properties of the HV NMOS transistor for these different substrates and
for different layouts are compared. HV NMOS transistor has been
successfully fabricated for IC/MEMS integration on SOI.
| Original language | English |
|---|---|
| Pages (from-to) | 110 - 112 |
| Number of pages | 3 |
| Journal | Physica Scripta |
| Volume | T114 |
| DOIs | |
| Publication status | Published - 2004 |
| MoE publication type | A1 Journal article-refereed |
| Event | 20th Nordic Semiconductor Meeting, NSM20 - Tampere, Finland Duration: 25 Aug 2003 → 27 Aug 2003 |