Implementation aspects of fault-tolerant logic built with single-electron devices

Jacek Flak; Mika Laiho

doi:10.1109/NORCHP.2009.5397816

Implementation aspects of fault-tolerant logic built with single-electron devices

University of Turku

Research output: Chapter in Book/Report/Conference proceeding › Conference article in proceedings › Scientific › peer-review

2 Citations (Scopus)

Abstract

This paper presents a single-electron tunneling (SET) device implementation of gates needed to build a nanoscale logic array for fault-tolerant computing. The proposed architecture is based on a regular array of locally interconnected SET gates controlled by CMOS peripheries. Embedded hardware and information redundancies help to surmount the limited reliability of nanodevices. Such a logic system can be versatile due to binary programmable interconnections. Gate structures designed for SET technology are presented and their simulation results are discussed.

Original language	English
Title of host publication	Proceedings of 2009 NORCHIP. Trondheim, Norway, 16 - 17 Nov. 2009
Publisher	IEEE Institute of Electrical and Electronic Engineers
Number of pages	4
ISBN (Electronic)	978-1-4244-4311-6
ISBN (Print)	978-1-4244-4310-9
DOIs	https://doi.org/10.1109/NORCHP.2009.5397816
Publication status	Published - 2009
MoE publication type	A4 Article in a conference publication
Event	2009 NORCHIP Conference - Trondheim, Norway Duration: 16 Nov 2009 → 17 Nov 2009

Conference

Conference	2009 NORCHIP Conference
Country/Territory	Norway
City	Trondheim
Period	16/11/09 → 17/11/09

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10.1109/NORCHP.2009.5397816

Cite this

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title = "Implementation aspects of fault-tolerant logic built with single-electron devices",

abstract = "This paper presents a single-electron tunneling (SET) device implementation of gates needed to build a nanoscale logic array for fault-tolerant computing. The proposed architecture is based on a regular array of locally interconnected SET gates controlled by CMOS peripheries. Embedded hardware and information redundancies help to surmount the limited reliability of nanodevices. Such a logic system can be versatile due to binary programmable interconnections. Gate structures designed for SET technology are presented and their simulation results are discussed.",

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AB - This paper presents a single-electron tunneling (SET) device implementation of gates needed to build a nanoscale logic array for fault-tolerant computing. The proposed architecture is based on a regular array of locally interconnected SET gates controlled by CMOS peripheries. Embedded hardware and information redundancies help to surmount the limited reliability of nanodevices. Such a logic system can be versatile due to binary programmable interconnections. Gate structures designed for SET technology are presented and their simulation results are discussed.

U2 - 10.1109/NORCHP.2009.5397816

DO - 10.1109/NORCHP.2009.5397816

M3 - Conference article in proceedings

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PB - IEEE Institute of Electrical and Electronic Engineers

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Y2 - 16 November 2009 through 17 November 2009

ER -

Implementation aspects of fault-tolerant logic built with single-electron devices

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