Abstract
In this lecture we will give a short overview of benefits and problems
of single chip designs in PRAM implementation, describe a single chip sparse
mesh based EREW PRAM architecture as well as exten-sions of it realizing the
CRCW PRAM and arbitrary ordered multioperation CRCW PRAM models. So-me
simulation results are provided.
| Original language | English |
|---|---|
| Publication status | Published - 2007 |
| MoE publication type | Not Eligible |
| Event | Advanced Parallel Programming: Models, Languages, Algorithms course - University of Linköping, Linköping, Sweden Duration: 5 Mar 2007 → 5 Mar 2007 |
Course
| Course | Advanced Parallel Programming |
|---|---|
| Country/Territory | Sweden |
| City | Linköping |
| Period | 5/03/07 → 5/03/07 |
Keywords
- Parallel computing
- PRAM
- MP-SOC
- CMP