Implementing PRAM on a Chip: Guest lecture

    Research output: Contribution to conferenceOther conference contributionProfessional

    Abstract

    In this lecture we will give a short overview of benefits and problems of single chip designs in PRAM implementation, describe a single chip sparse mesh based EREW PRAM architecture as well as exten-sions of it realizing the CRCW PRAM and arbitrary ordered multioperation CRCW PRAM models. So-me simulation results are provided.
    Original languageEnglish
    Publication statusPublished - 2007
    MoE publication typeNot Eligible
    EventAdvanced Parallel Programming: Models, Languages, Algorithms course - University of Linköping, Linköping, Sweden
    Duration: 5 Mar 20075 Mar 2007

    Course

    CourseAdvanced Parallel Programming
    CountrySweden
    CityLinköping
    Period5/03/075/03/07

    Keywords

    • Parallel computing
    • PRAM
    • MP-SOC
    • CMP

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