Improved neuron MOS-transistor structures for integrated neural network circuits

Arto Rantala, Sami Franssila, Kimmo Kaski, Jouko Lampinen, Markku Åberg, Pekka Kuivalainen

    Research output: Contribution to journalArticle in a proceedings journalScientificpeer-review

    13 Citations (Scopus)

    Abstract

    The neuron MOS transistor is a recently discovered device which is capable of executing a weighted sum calculation of multiple input signals and threshold operation based on the result of summation, thereby simulating the function of biological neurons. A comprehensive set of neuron test transistors has been designed, where a number of input gates are coupled capacitively to a floating gate, which controls the channel current. Integrated circuits for neural network applications have also been designed, based on the neuron MOS transistors. These circuits include neuron CMOS inverters and A/D and D/A converters. To increase the accuracy of the neuron MOSFET structures, calibration techniques are proposed and tested. All the test structures and circuits are implemented by using a standard 0.8 μm double-polysilicon CMOS technology. Attention was paid to saving the layout area and reducing power consumption.
    Original languageEnglish
    Pages (from-to)25-34
    JournalIEE Proceedings: Circuits, Devices and Systems
    Volume148
    Issue number1
    DOIs
    Publication statusPublished - 2001
    MoE publication typeA4 Article in a conference publication

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