The neuron MOS transistor is a recently discovered device which is capable of executing a weighted sum calculation of multiple input signals and threshold operation based on the result of summation, thereby simulating the function of biological neurons. A comprehensive set of neuron test transistors has been designed, where a number of input gates are coupled capacitively to a floating gate, which controls the channel current. Integrated circuits for neural network applications have also been designed, based on the neuron MOS transistors. These circuits include neuron CMOS inverters and A/D and D/A converters. To increase the accuracy of the neuron MOSFET structures, calibration techniques are proposed and tested. All the test structures and circuits are implemented by using a standard 0.8 μm double-polysilicon CMOS technology. Attention was paid to saving the layout area and reducing power consumption.
Rantala, A., Franssila, S., Kaski, K., Lampinen, J., Åberg, M., & Kuivalainen, P. (2001). Improved neuron MOS-transistor structures for integrated neural network circuits. IEE Proceedings: Circuits, Devices and Systems, 148(1), 25-34. https://doi.org/10.1049/ip-cds:20010055