Increased Breakdown Voltage in Vertical Heterostructure III-V Nanowire MOSFETs with a Field Plate

Olli Pekka Kilpi, Stefan Andric, Johannes Svensson, Mamidala Saketh Ram, Erik Lind, Lars Erik Wernersson

Research output: Contribution to journalArticleScientificpeer-review

2 Citations (Scopus)


Vertical III-V heterostructure MOSFETs exhibit outstanding performance at reduced supply voltages. In this letter, we report on a novel process of extending high-speed device operation towards higher voltages. The device vertical geometry allows for engineering a field plate by covering the nanowire drain area with a 10-nm-thick SiO2 film. The film acts as a field moderator in the device drain region. Reference devices without a field plate exhibit a transconductance of 2.5 mS/ $\mu \text{m}$ , while devices with a 120-nm-long field plate show 1.5 mS/ $\mu \text{m}$ but a three times increase in breakdown voltage. Measurements show that the field-screening effect attributes to reduced band-to-band tunneling and impact ionization, thereby reducing the parasitic bipolar effect in the MOSFET channel as well. The devices show promise in applications in circuits and systems requiring large power-handling.

Original languageEnglish
Pages (from-to)1596 - 1598
Number of pages3
JournalIEEE Electron Device Letters
Issue number11
Publication statusPublished - 1 Nov 2021
MoE publication typeA1 Journal article-refereed


  • Breakdown
  • Electric breakdown
  • Field plate
  • Heterostructure
  • InAs
  • InGaAs
  • Logic gates
  • Nanoscale devices
  • Nanowire
  • Performance evaluation
  • Transconductance
  • Transistors
  • Vertical


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