Integration and Packaging of Optoelectronic and Silicon Photonic Chips on a µm-scale SOI Platform

Timo Aalto; Mikko Harjanne; Markku Kapulainen; Sami Ylinen

Integration and Packaging of Optoelectronic and Silicon Photonic Chips on a µm-scale SOI Platform

Research output: Chapter in Book/Report/Conference proceeding › Conference article in proceedings › Professional

Abstract

An overview of an integration platform with 1–10 µm thick silicon-on-insulator waveguides is given. It is suitable for the integration and packaging of optoelectronic and silicon photonic (nm-scale) chips. The platform can also contain many passive functions, such as spot-size converters, couplers, wavelength (de)multiplexers/filters and polarization splitters. The footprint of the platform is minimized by using multi-step patterning to realize e.g. mirrors and short MMI couplers

Original language	English
Title of host publication	European Conference on Integrated Photonics website
Number of pages	2
Publication status	Published - 2012
MoE publication type	D3 Professional conference proceedings
Event	16th European Conference on Integrated Optics ECIO 2012 - Sitges, Barcelona, Spain Duration: 18 Apr 2012 → 20 Apr 2012

Conference

Conference	16th European Conference on Integrated Optics ECIO 2012
Country/Territory	Spain
City	Barcelona
Period	18/04/12 → 20/04/12

Keywords

Silicon-on-insulator
SOI
integration platform
silicon photonics
optoelectronics
hybrid integration
packaging

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https://www.ecio-conference.org/wp-content/uploads/2016/05/2012/ECIO-2012_ThP128.pdf

Cite this

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title = "Integration and Packaging of Optoelectronic and Silicon Photonic Chips on a µm-scale SOI Platform",

abstract = "An overview of an integration platform with 1–10 µm thick silicon-on-insulator waveguides is given. It is suitable for the integration and packaging of optoelectronic and silicon photonic (nm-scale) chips. The platform can also contain many passive functions, such as spot-size converters, couplers, wavelength (de)multiplexers/filters and polarization splitters. The footprint of the platform is minimized by using multi-step patterning to realize e.g. mirrors and short MMI couplers",

keywords = "Silicon-on-insulator, SOI, integration platform, silicon photonics, optoelectronics, hybrid integration, packaging",

author = "Timo Aalto and Mikko Harjanne and Markku Kapulainen and Sami Ylinen",

note = "CA2: TK610 SDA: MEL; 16th European Conference on Integrated Optics ECIO 2012 ; Conference date: 18-04-2012 Through 20-04-2012",

year = "2012",

language = "English",

booktitle = "European Conference on Integrated Photonics website",

}

Aalto, T , Harjanne, M , Kapulainen, M & Ylinen, S 2012, Integration and Packaging of Optoelectronic and Silicon Photonic Chips on a µm-scale SOI Platform. in European Conference on Integrated Photonics website., ThP128, 16th European Conference on Integrated Optics ECIO 2012, Barcelona, Spain, 18/04/12. <https://www.ecio-conference.org/wp-content/uploads/2016/05/2012/ECIO-2012_ThP128.pdf>

TY - GEN

T1 - Integration and Packaging of Optoelectronic and Silicon Photonic Chips on a µm-scale SOI Platform

AU - Aalto, Timo

AU - Harjanne, Mikko

AU - Kapulainen, Markku

AU - Ylinen, Sami

N1 - CA2: TK610 SDA: MEL

PY - 2012

Y1 - 2012

N2 - An overview of an integration platform with 1–10 µm thick silicon-on-insulator waveguides is given. It is suitable for the integration and packaging of optoelectronic and silicon photonic (nm-scale) chips. The platform can also contain many passive functions, such as spot-size converters, couplers, wavelength (de)multiplexers/filters and polarization splitters. The footprint of the platform is minimized by using multi-step patterning to realize e.g. mirrors and short MMI couplers

AB - An overview of an integration platform with 1–10 µm thick silicon-on-insulator waveguides is given. It is suitable for the integration and packaging of optoelectronic and silicon photonic (nm-scale) chips. The platform can also contain many passive functions, such as spot-size converters, couplers, wavelength (de)multiplexers/filters and polarization splitters. The footprint of the platform is minimized by using multi-step patterning to realize e.g. mirrors and short MMI couplers

KW - Silicon-on-insulator

KW - SOI

KW - integration platform

KW - silicon photonics

KW - optoelectronics

KW - hybrid integration

KW - packaging

M3 - Conference article in proceedings

BT - European Conference on Integrated Photonics website

T2 - 16th European Conference on Integrated Optics ECIO 2012

Y2 - 18 April 2012 through 20 April 2012

ER -

Integration and Packaging of Optoelectronic and Silicon Photonic Chips on a µm-scale SOI Platform

Abstract

Conference

Keywords

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