ITO Contact Optimization for Enhancement Mode BEOL MOSFETs

Monolithically integrated active components that are post-CMOS compatible enable to shift several functionalities to the back-end-of-line (BEOL), for example; power gating, voltage regulation, analog RF transistors, and non-volatilememories (NVM). This approach could offer both higher performance and overall denser integration. Oxide semiconductors (OS), such as tin-doped-InO x (ITO), represent an interesting set of materials for BEOL integration as they, compared to Si and Si-on-insulator (SOI), have advantageous electrical properties and can be deposited onto many different types of surfaces at low temperatures (low-T), using physical vapor deposition (PVD) or atomic layer deposition (ALD). The spherical symmetry of the s-orbital dominated conductance makes OSs insensitive to roughness and defects [1], allowing high mobility (μFE > 100 cm² V^-1 s^-1) for thin films (>1.5 nm) [2]. Further, the wide bandgap and low achievable contact resistances (R_C), combined with the relatively shallow electric field penetration depth due to low permittivity, means that high performance can be achieved with very aggressively scaled devices [3]. Demonstrations show large ON/OFF-current (I_on/I_off) ratios of 10¹⁰ for a channel length (L_G) of 10 nm [4], and high I_on of 3.1 mA/μm for 0.5 V drain-source-voltage (V_DS) [2]. The best demonstrated contact resistance reaches the quantum limit at R_c=23.4 Ωμm, with a negative Schottky barrier due to trap-induced positive charges at the InO_x contact interface [5], improving on the previous record low R_C of 162Ωμm for ITO [4]. It is further laid out that a 2D carrier density of ∼ 2 · 10¹³ cm^-2 is needed to reach quantum limit resistance, which for the devices in the study, pushes the threshold voltage (V_T) into deep negative bias [4]. In this work, we show how a low RC can be combined with enhancement operation.