Low noise 0.9 GHz FBAR clock

Markku Åberg, Miikka Ylimaula, Markku Ylilammi, Tuomas Pensala, Arto Rantala

    Research output: Chapter in Book/Report/Conference proceedingConference article in proceedingsScientificpeer-review

    2 Citations (Scopus)

    Abstract

    A low noise 0.9GHz FBAR clock consisting of an oscillator and divider circuit for single sided-to-differential conversion for high-speed A/D-converter was designed, realized with an in-house FBAR and a commercial 0.35 /spl mu/m CMOS process, and tested. The circuit showed very good jitter and phase noise performance.
    Original languageEnglish
    Title of host publication2005 NORCHIP
    PublisherIEEE Institute of Electrical and Electronic Engineers
    Pages257-260
    ISBN (Print)1-4244-0064-3, 978-1-4244-0064-5
    DOIs
    Publication statusPublished - 2005
    MoE publication typeA4 Article in a conference publication
    Event23rd Norchip Conference, IEEE NORCHIP 2005 - Oulu, Finland
    Duration: 21 Nov 200522 Nov 2005

    Conference

    Conference23rd Norchip Conference, IEEE NORCHIP 2005
    CountryFinland
    CityOulu
    Period21/11/0522/11/05

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  • Cite this

    Åberg, M., Ylimaula, M., Ylilammi, M., Pensala, T., & Rantala, A. (2005). Low noise 0.9 GHz FBAR clock. In 2005 NORCHIP (pp. 257-260). IEEE Institute of Electrical and Electronic Engineers. https://doi.org/10.1109/NORCHP.2005.1597038