Abstract
A low noise 0.9GHz FBAR clock consisting of an oscillator and divider circuit for single sided-to-differential conversion for high-speed A/D-converter was designed, realized with an in-house FBAR and a commercial 0.35 /spl mu/m CMOS process, and tested. The circuit showed very good jitter and phase noise performance.
Original language | English |
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Title of host publication | 2005 NORCHIP |
Publisher | IEEE Institute of Electrical and Electronic Engineers |
Pages | 257-260 |
ISBN (Print) | 978-1-4244-0064-5 |
DOIs | |
Publication status | Published - 2005 |
MoE publication type | A4 Article in a conference publication |
Event | 23rd Norchip Conference, IEEE NORCHIP 2005 - Oulu, Finland Duration: 21 Nov 2005 → 22 Nov 2005 |
Conference
Conference | 23rd Norchip Conference, IEEE NORCHIP 2005 |
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Country/Territory | Finland |
City | Oulu |
Period | 21/11/05 → 22/11/05 |